Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 8/08/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Resampler Intel® FPGA IP 11. Clipper Intel® FPGA IP 12. Clocked Video Input Intel® FPGA IP 13. Clocked Video to Full-Raster Converter Intel® FPGA IP 14. Clocked Video Output Intel® FPGA IP 15. Color Space Converter Intel® FPGA IP 16. Deinterlacer Intel® FPGA IP 17. FIR Filter Intel® FPGA IP 18. Frame Cleaner Intel® FPGA IP 19. Full-Raster to Clocked Video Converter Intel® FPGA IP 20. Full-Raster to Streaming Converter Intel® FPGA IP 21. Generic Crosspoint Intel® FPGA IP 22. Genlock Signal Router Intel® FPGA IP 23. Guard Bands Intel® FPGA IP 24. Mixer Intel® FPGA IP 25. Pixels in Parallel Converter Intel® FPGA IP 26. Scaler Intel® FPGA IP 27. Tone Mapping Operator Intel® FPGA IP 28. Test Pattern Generator Intel® FPGA IP 29. Video Frame Buffer Intel® FPGA IP 30. Video Streaming FIFO Intel® FPGA IP 31. Video Timing Generator Intel® FPGA IP 32. Warp Intel® FPGA IP 33. Design Security 34. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Resampler Intel® FPGA IP x
10.1. About the Chroma Resampler IP 10.2. Chroma Resampler IP Parameters 10.3. Chroma Resampler IP Functional Description 10.4. Chroma Resampler IP Registers 10.5. Chroma Resampler IP Software API
10.1. About the Chroma Resampler IP x
10.1.1. Chroma Resampler Performance and Resources
10.3. Chroma Resampler IP Functional Description x
10.3.1. Chroma Resampler IP Interfaces
11. Clipper Intel® FPGA IP x
11.1. About the Clipper IP 11.2. Clipper IP Parameters 11.3. Clipper IP Interfaces 11.4. Clipper IP Registers 11.5. Clipper IP Software API
11.1. About the Clipper IP x
11.1.1. Clipper IP Performance and Resources
12. Clocked Video Input Intel® FPGA IP x
12.1. About the Clocked Video Input IP 12.2. Initializing the Clocked Video Input IP 12.3. Clocked Video Input IP Parameters 12.4. Clocked Video Input IP Interfaces 12.5. Clocked Video Input IP Registers 12.6. Clocked Video Input IP Software API
12.1. About the Clocked Video Input IP x
12.1.1. Clocked Video Input IP Features 12.1.2. Clocked Video Input IP Performance and Resources
13. Clocked Video to Full-Raster Converter Intel® FPGA IP x
13.1. About the Clocked Video to Full-Raster Converter IP 13.2. Clocked Video to Full-Raster Converter Parameters 13.3. Clocked Video to Full-Raster Converter Block Description 13.4. Clocked Video Converter to Full-Raster IP Registers
13.1. About the Clocked Video to Full-Raster Converter IP x
13.1.1. Clocked Video to Full-Raster Converter Features 13.1.2. Clocked Video to Full-Raster Converter Performance and Resources
13.3. Clocked Video to Full-Raster Converter Block Description x
13.3.1. Clocked Video to Full-Raster Converter Interfaces
14. Clocked Video Output Intel® FPGA IP x
14.1. About the Clocked Video Output IP 14.2. Clocked Video Output IP Parameters 14.3. Clocked Video Output IP Functional Description 14.4. Clocked Video Output IP Interfaces 14.5. Clocked Video Output IP Registers 14.6. Clocked Video Output IP Software API
14.1. About the Clocked Video Output IP x
14.1.1. Clocked Video Output IP Performance and Resources 14.1.2. Clocked Video Output IP Features
15. Color Space Converter Intel® FPGA IP x
15.1. About the Color Space Converter IP 15.2. Color Space Converter IP Parameters 15.3. Color Space Converter IP Functional Description 15.4. Color Space Converter IP Registers 15.5. Color Space Converter IP Software API
15.1. About the Color Space Converter IP x
15.1.1. Color Space Converter IP Features 15.1.2. Color Space Converter IP Performance and Resources
15.3. Color Space Converter IP Functional Description x
15.3.1. Color Space Converter IP Interfaces
16. Deinterlacer Intel® FPGA IP x
16.1. About the Deinterlacer IP 16.2. Deinterlacer Parameters 16.3. Deinterlacer Interfaces 16.4. Deinterlacer Registers 16.5. Deinterlacer IP Software API
16.1. About the Deinterlacer IP x
16.1.1. Deinterlacer Performance and Resources
17. FIR Filter Intel® FPGA IP x
17.1. About the FIR Filter 17.2. FIR Filter Parameters 17.3. FIR Filter IP Operation 17.4. FIR Filter Interfaces 17.5. FIR Filter Registers 17.6. FIR Filter IP Software API
17.3. FIR Filter IP Operation x
17.3.1. FIR Filter Processing 17.3.2. FIR Filter Precision 17.3.3. FIR Coefficient Specification 17.3.4. FIR Filter Symmetry 17.3.5. Result to Output Data Type Conversion
17.3.4. FIR Filter Symmetry x
17.3.4.1. No Symmetry 17.3.4.2. Horizontal Symmetry 17.3.4.3. Vertical Symmetry 17.3.4.4. Horizontal and Vertical Symmetry 17.3.4.5. Diagonal Symmetry
18. Frame Cleaner Intel® FPGA IP x
18.1. About the Frame Cleaner IP 18.2. Frame Cleaner IP Parameters 18.3. Frame Cleaner IP Functional Description 18.4. Frame Cleaner IP Interfaces 18.5. Frame Cleaner IP Registers 18.6. Frame Cleaner IP Software API
18.1. About the Frame Cleaner IP x
18.1.1. Frame Cleaner IP Performance and Resources
19. Full-Raster to Clocked Video Converter Intel® FPGA IP x
19.1. About the Full-Raster to Clocked Video Converter 19.2. Full Raster to Clocked Video Converter Parameters 19.3. Full-Raster to Clocked Video Converter Block Description 19.4. Full-Raster to Clocked Video Converter Registers
19.1. About the Full-Raster to Clocked Video Converter x
19.1.1. Full-Raster to Clocked Video Converter Features 19.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
19.3. Full-Raster to Clocked Video Converter Block Description x
19.3.1. Full Raster to Clocked Video Converter Interfaces
20. Full-Raster to Streaming Converter Intel® FPGA IP x
20.1. About the Full-Raster to Streaming Converter IP 20.2. Full-Raster to Streaming Converter Parameters 20.3. Full-Raster to Streaming Converter Block Description
20.1. About the Full-Raster to Streaming Converter IP x
20.1.1. Full-Raster to Streaming Converter Features 20.1.2. Full-Raster to Streaming Converter Performance and Resources
20.3. Full-Raster to Streaming Converter Block Description x
20.3.1. Full-Raster to Streaming Converter Interfaces
21. Generic Crosspoint Intel® FPGA IP x
21.1. About the Generic Crosspoint IP 21.2. Generic Crosspoint IP Parameters 21.3. Generic Crosspoint IP Interfaces 21.4. Generic Crosspoint IP Registers 21.5. Generic Crosspoint IP Software API
21.1. About the Generic Crosspoint IP x
21.1.1. Generic Crosspoint IP Features 21.1.2. Generic Crosspoint Performance and Resources
22. Genlock Signal Router Intel® FPGA IP x
22.1. About the Genlock Signal Router IP 22.2. Genlock Signal Router IP Parameters 22.3. Genlock Signal Router IP Interfaces 22.4. Genlock Signal Router IP Registers 22.5. Genlock Signal Router IP Software API
22.1. About the Genlock Signal Router IP x
22.1.1. Genlock Signal Router IP Features 22.1.2. Genlock Signal Router IP Performance and Resources
23. Guard Bands Intel® FPGA IP x
23.1. About the Guard Bands IP 23.2. Guard Bands IP Parameters 23.3. Guard Bands IP Interfaces 23.4. Guard Bands IP Registers 23.5. Guard Bands IP Software API
23.1. About the Guard Bands IP x
23.1.1. Guard Bands IP Performance and Resources
24. Mixer Intel® FPGA IP x
24.1. About the Mixer IP 24.2. Mixer IP Parameters 24.3. Mixer IP Functional Description 24.4. Mixer IP Registers 24.5. Mixer IP Software API
24.1. About the Mixer IP x
24.1.1. Mixer IP Performance and Resources
24.3. Mixer IP Functional Description x
24.3.1. Mixer IP Interfaces
25. Pixels in Parallel Converter Intel® FPGA IP x
25.1. About the Pixels in Parallel Converter IP 25.2. Pixels in Parallel IP Converter Parameters 25.3. Pixels in Parallel Converter Interfaces 25.4. Pixels in Parallel Converter Registers 25.5. Pixels in Parallel Converter IP Software API
25.1. About the Pixels in Parallel Converter IP x
25.1.1. Pixels in Parallel IP Converter Performance and Resources
26. Scaler Intel® FPGA IP x
26.1. About the Scaler 26.2. Scaler IP Parameters 26.3. Scaler IP Functional Description 26.4. Scaler IP Registers 26.5. Scaler IP Software API
26.1. About the Scaler x
26.1.1. Scaler IP Performance and Resources
26.2. Scaler IP Parameters x
26.2.1. Updating Scaler IP Runtime Coefficients 26.2.2. Scaler Maximum Resolution
26.3. Scaler IP Functional Description x
26.3.1. Partial Frame Scaling 26.3.2. Scaler IP Interfaces
27. Tone Mapping Operator Intel® FPGA IP x
27.1. About the Tone Mapping Operator IP 27.2. TMO IP Parameters 27.3. TMO IP Block Description 27.4. TMO IP Registers 27.5. TMO IP Software API
27.1. About the Tone Mapping Operator IP x
27.1.1. TMO IP Features 27.1.2. TMO IP Performance and Resource Utilization
27.3. TMO IP Block Description x
27.3.1. TMO IP Interfaces 27.3.2. TMO IP Latency
28. Test Pattern Generator Intel® FPGA IP x
28.1. About the Test Pattern Generator IP 28.2. Test Pattern Generator IP Parameters 28.3. Test Pattern Generator IP Functional Description 28.4. Test Pattern Generator IP Registers 28.5. Test Pattern Generator IP Software API
28.1. About the Test Pattern Generator IP x
28.1.1. Test Pattern Generator IP Performance and Resources
28.3. Test Pattern Generator IP Functional Description x
28.3.1. Test Pattern Generator IP Interfaces
29. Video Frame Buffer Intel® FPGA IP x
29.1. About the Video Frame Buffer IP 29.2. Video Frame Buffer IP Parameters 29.3. Video Frame Buffer IP Functional Description 29.4. Video Frame Buffer IP Registers 29.5. Video Frame Buffer IP Software API
29.1. About the Video Frame Buffer IP x
29.1.1. Video Frame Buffer Performance and Resources
29.3. Video Frame Buffer IP Functional Description x
29.3.1. Video Frame Buffer IP Interfaces
30. Video Streaming FIFO Intel® FPGA IP x
30.1. About the Video Streaming FIFO IP 30.2. Video Streaming FIFO IP Parameters 30.3. Video Streaming FIFO IP Interfaces
30.1. About the Video Streaming FIFO IP x
30.1.1. Video Streaming FIFO IP Performance and Resources
31. Video Timing Generator Intel® FPGA IP x
31.1. About the Video Timing Generator IP 31.2. Video Timing Generator IP Parameters 31.3. Video Timing Generator IP Functional Description 31.4. Video Timing Generator IP Interfaces 31.5. Video Timing Generator IP Registers 31.6. Video Timing Generator IP Software API
31.1. About the Video Timing Generator IP x
31.1.1. Video Timing Generator IP Features 31.1.2. Video Timing Generator IP Performance and Resources
32. Warp Intel® FPGA IP x
32.1. About the Warp IP 32.2. Warp IP Parameters 32.3. Warp IP Block Description 32.4. Warp IP Registers 32.5. Warp IP Software API
32.1. About the Warp IP x
32.1.1. Warp IP Features 32.1.2. Warp IP Performance and Resource Utilization
32.3. Warp IP Block Description x
32.3.1. Warp IP Interfaces 32.3.2. Warp IP Latency 32.3.3. External Memory for Warp IP
32.5. Warp IP Software API x
32.5.1. Using Warp IP Software 32.5.2. Warp IP Software Code Examples UHD 60 Hz Workflow example Warp mesh usage Easy warp example Warp latency parameters generation example
33. Design Security x
33.1. Memory Subsystems 33.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide

32.5.2. Warp IP Software Code Examples

UHD 60 Hz Workflow example

This example shows the workflow and basic warp software usage of the C++ source code to generate and apply 15 degree rotation warp. The example is for 3840x2160@60Hz video, which requires the processing to be split between two warp engines. The frame buffer and warp coefficient base addresses in the example are arbitrary. Actual values depend on your particular system design. 

const uint32_t FRAMEBUF_BASE_ADDR	= 0x80000000;
const uint32_t COEF_BASE_ADDR		= 0xa0000000;
intel_vvp_warp_base_t base			= INTEL_VVP_WARP_BASE;
intel_vvp_warp_instance_t wrp0;

// Warp data sizes should be multiples of 256kb
auto align_256k = [](const uint32_t addr)->uint32_t
{
	static const uint32_t DATA_SIZE_256KB = (256 * 1024);
	return ((addr + DATA_SIZE_256KB - 1) & ~(DATA_SIZE_256KB - 1));
};

// Initialize driver instance
intel_vvp_warp_init_instance(&wrp0, base);

intel_vvp_warp_channel_t* ch0 = intel_vvp_warp_create_double_channel(&wrp0, 0, 0, 1, 0);

// Fill in warp channel configuration structure
intel_vvp_warp_channel_config_t cfg;

cfg.ram_addr = FRAMEBUF_BASE_ADDR;	// Frame buffers base address
cfg.cs = ERGB_FULL;					// Video colourspace
cfg.scan = EMEGABLOCK;				// Scan pattern
cfg.width_input = 3840;				// Video dimensions
cfg.height_input = 2160;
cfg.width_output = 3840;
cfg.height_output = 2160;
cfg.lfr = 0;						// No low frame rate fallback

// Configure warp channel using the parameters above
intel_vvp_warp_configure_channel(ch0, &cfg);

// Instantiate and initialize mesh generator
WarpConfigurator configurator;
configurator.SetInputResolution(3840, 2160);
configurator.SetOutputResolution(3840, 2160);
configurator.Reset();
configurator.SetRotate(15.0f);

// Generate mesh
WarpMeshPtr mesh = configurator.GenerateMeshFromFixed();
WarpMeshSet mesh_set{ mesh };

// Instantiate data generator
WarpDataGenerator data_generator;
// Obtain required hardware information
WarpHwContextPtr hw = WarpDataHelper::GetHwContext(ch0);

WarpDataContext ctx{
	hw,
	3840, 2160,
	3840, 2160
};

// Generate warp data using provided hardware configuration and mesh
WarpDataPtr user_data = data_generator.GenerateData(ctx, mesh_set);

// Allocate and fill in intel_vvp_warp_data_t object for the required number of engines
const uint32_t warp_data_size = sizeof(intel_vvp_warp_data_t) + user_data->GetEngines() * sizeof(intel_vvp_warp_engine_data_t);
intel_vvp_warp_data_t* warp_data = (intel_vvp_warp_data_t*)malloc(warp_data_size);

warp_data->num_engines = user_data->GetEngines();
intel_vvp_warp_engine_data_t* engine_data = warp_data->engine_data;
const uint32_t mesh_stride = ctx._engine_mesh_stride / 4 - 1; // Mesh nodes in multiples of 4 less 1

// Processing is split between two engines
// 1st engine processes left half of the frame
{
	engine_data[0].start_h = 0;
	engine_data[0].start_v = 0;
	engine_data[0].end_h = ctx._engine_hblocks - 1;
	engine_data[0].end_v = ctx._vblocks_out - 1;
	engine_data[0].mesh_stride = mesh_stride;

	const WarpEngineData* ue = user_data->GetEngineData(0);

	const uint32_t mesh_data_size = ue->GetMeshEntries() * sizeof(mesh_entry_t);
	const uint32_t filter_data_size = ue->GetFilterEntries() * sizeof(filter_entry_t);
	const uint32_t fetch_data_size = ue->GetFilterEntries() * sizeof(fetch_entry_t);
	
	// Point engine to the location of the mesh, filter and fetch data
	engine_data[0].mesh_addr = COEF_BASE_ADDR;
	engine_data[0].filter_addr = engine_data[0].mesh_addr + align_256k(mesh_data_size);
	engine_data[0].fetch_addr = engine_data[0].filter_addr + align_256k(filter_data_size);

	// Transfer generated warp data to the calculated destination
	memcpy((void*)(engine_data[0].mesh_addr),	ue->GetMeshData(),		mesh_data_size);
	memcpy((void*)(engine_data[0].filter_addr),	ue->GetFilterData(),	filter_data_size);
	memcpy((void*)(engine_data[0].fetch_addr),	ue->GetFetchData(),		fetch_data_size);
}
// 2nd engine - right half of the frame
{
	engine_data[1].start_h = ctx._engine_hblocks;
	engine_data[1].start_v = 0; engine_data[1].end_h = ctx._hblocks_out - 1;
	engine_data[1].end_v = ctx._vblocks_out - 1;
	engine_data[1].mesh_stride = mesh_stride;

	const WarpEngineData* ue = user_data->GetEngineData(1);

	const uint32_t mesh_data_size = ue->GetMeshEntries() * sizeof(mesh_entry_t);
	const uint32_t filter_data_size = ue->GetFilterEntries() * sizeof(filter_entry_t);
	const uint32_t fetch_data_size = ue->GetFetchEntries() * sizeof(fetch_entry_t);

	// Point engine to the location of the mesh, filter and fetch data
	engine_data[1].mesh_addr = engine_data[0].fetch_addr + align_256k(user_data->GetEngineData(0)->_fetch_entries * sizeof(fetch_entry_t));
	engine_data[1].filter_addr = engine_data[1].mesh_addr + align_256k(mesh_data_size);
	engine_data[1].fetch_addr = engine_data[1].filter_addr + align_256k(filter_data_size);

	// Transfer generated warp data to the calculated destination
	memcpy((void*)(engine_data[1].mesh_addr),	ue->GetMeshData(),		mesh_data_size);
    memcpy((void*)(engine_data[1].filter_addr),	ue->GetFilterData(),	filter_data_size);
	memcpy((void*)(engine_data[1].fetch_addr),	ue->GetFetchData(),		fetch_data_size);
}

warp_data->_skip_megablock_data = user_data->GetSkipMegablockData();
warp_data->_skip_ram_page = 0;

// Apply warp by passing new warp data set to the driver
intel_vvp_warp_apply_transform(ch0, warp_data);

// Release allocated resources
free(warp_data);
intel_vvp_warp_free_channel(ch0);

Warp mesh usage

Define required warp using the WarpMesh object. The example shows the simplest case of 1:1 (unity) warp for a 3840x2160 video. 

intel_vvp_warp::WarpMesh mesh{3840, 2160};

for(uint32_t v = 0; v < mesh.GetVNodes(); ++v)
{
	mesh_node_t* node = mesh.GetRow(v);

	for(uint32_t h = 0; h < mesh.GetHNodes(); ++h)
	{
					  node->_x = (h * mesh.GetStep()) << 4;
		  node->_y = (v * mesh.GetStep()) << 4;
	}
}

Mesh coordinates use the least significant four bits as fractional part for subpixel precision. In the example above the fractional part is always 0. Store subpixel positions in the following way: 

mesh_node_t* node = mesh.GetRow(v);
…
float pos_x = 10.6f;
node->_x = static_cast<int32_t>(roundf(pos_x * 16.0f));

Easy warp example

When you turn on Easy warp you can rotate the input video to 0, 90, 180 or 270 degrees or mirror the video without the need of transform mesh and associated warp data. 


const uint32_t FRAMEBUF_BASE_ADDR	= 0x80000000;
const uint32_t width			= 1920;
const uint32_t height			= 1080;
intel_vvp_warp_base_t base		= INTEL_VVP_WARP_BASE;
intel_vvp_warp_instance wrp0;

// Initialize driver instance
intel_vvp_warp_init_instance(&wrp0, base);

// Allocate Easy warp channel
intel_vvp_warp_channel_t* ch0 = intel_vvp_warp_create_easy_warp_channel(&wrp0, 0, 0);
assert(ch0 != NULL);
assert(intel_vvp_warp_check_easy_warp_capable(ch0) == 0);

// Configure channel
intel_vvp_warp_channel_config_t cfg;

// Configure in 4K, RGB Full colourspace
cfg.ram_addr = FRAMEBUF_BASE_ADDR;
cfg.cs = ERGB_FULL;
cfg.width_input = width;
cfg.height_input = height;
cfg.width_output = width;
cfg.height_output = height;
cfg.lfr = 0;

intel_vvp_warp_configure_channel(ch0, &cfg);	

// Mirror input video
// Enable video bypass, keep original resolution
intel_vvp_warp_bypass(ch0, 1, 0, width, height);
// Configure Easy warp mirror
intel_vvp_warp_set_easy_warp(ch0, 0x4);

// Rotate input video 90 degrees CCW
// Enable video bypass, flip input width and height
intel_vvp_warp_bypass(ch0, 1, 0, height, width);
// Configure Easy warp rotation
intel_vvp_warp_set_easy_warp(ch0, 0x01);	

// Release warp channel
intel_vvp_warp_free_channel(ch0);
assert(wrp0.num_engines > 0);

Warp latency parameters generation example

The example shows how to generate recommended minimum latency parameters for a given video transformation. These parameters are necessary to configure video pipeline for low latency operation. 


// Example video and system clock
static constexpr uint32_t EXAMPLE_CLOCK	= 300000000;
// UHD video dimensions
static constexpr uint32_t WIDTH_UHD		= 3840;
static constexpr uint32_t HEIGHT_UHD		= 2160;
static constexpr uint32_t FULL_HEIGHT_UHD	= 2250;
// Output frame rate x100
static constexpr uint32_t OUTPUT_FRAME_RATE	= 6000;

// In this example system and video clock are the same
const uint32_t system_clock = EXAMPLE_CLOCK;
const uint32_t video_clock = EXAMPLE_CLOCK;

// Warp channel
intel_vvp_warp_channel_t* ch0{nullptr};

// Allocate and initialize a warp channel here
//	...
//////////////////////////////////////////////

// Generate a 4K mesh for 5 degree CCW rotation
WarpConfigurator configurator{WarpDataHelper::GetHwContext(ch0)};

configurator.SetInputResolution(WIDTH_UHD, HEIGHT_UHD);
configurator.SetOutputResolution(WIDTH_UHD, HEIGHT_UHD);
configurator.Reset();
configurator.SetRotate(5.0f);

WarpMeshSet mesh_set{configurator.GenerateMeshFromFixed()};

// Parameters required for warp data generation
WarpDataContext ctx{
	WarpDataHelper::GetHwContext(ch0),
	WIDTH_UHD, HEIGHT_UHD,
	WIDTH_UHD, HEIGHT_UHD
};
			
WarpDataGenerator data_generator;

WarpDataPtr user_data = data_generator.GenerateData(ctx, mesh_set);

// Obtain latency params for the configured warp
WarpLatencyParams latency_params = data_generator.GenerateLatencyParams(ctx, user_data, system_clock, video_clock, FULL_HEIGHT_UHD, OUTPUT_FRAME_RATE);

// Upload and apply generated warp data here
// …
// intel_vvp_warp_apply_transform(ch0, …);
// …

// Pass on “output_latency” to the driver
intel_vvp_warp_set_output_latency(ch0, latency_params._output_latency);

// The “total_latency” member represents the recommended minimum offset
// between the input and output frames
// The value is in axi4s_vid_out_0_clock clock cycles
// Use the this parameter to configure the rest of the video pipeline
// as appropriate
//
//	latency_params._total_latency;
//assert(wrp0.num_engines > 0);
Level Two Title