OpenCL* Quick Start User Guide: Intel FPGA Programmable Acceleration Card D5005

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ID 683324
Date 7/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Setting Up the Host Machine 3. Running Diagnostics 4. OpenCL* Support for Multi-Card Systems 5. Running Samples 6. Compiling OpenCL* Kernels 7. Intel® FPGA PAC D5005 Security for OpenCL* Applications 8. Document Revision History for OpenCL* Quick Start User Guide
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary 1.3. Acronyms
2. Setting Up the Host Machine x
2.1. Introduction 2.2. Initializing the Environment for OpenCL* with Intel Acceleration Stack 2.3. Initializing the Intel® Acceleration Stack for OpenCL* in a Virtualized Environment
2.1. Introduction x
2.1.1. Release Content
5. Running Samples x
5.1. Running Hello World 5.2. Running Vector Add
6. Compiling OpenCL* Kernels x
6.1. Checking Timing Results
1. About this Document
2. Setting Up the Host Machine
3. Running Diagnostics
4. OpenCL* Support for Multi-Card Systems
5. Running Samples
6. Compiling OpenCL* Kernels
7. Intel® FPGA PAC D5005 Security for OpenCL* Applications
8. Document Revision History for OpenCL* Quick Start User Guide

1.2. Acceleration Glossary

Table 2.  Acceleration Stack for Intel® Xeon® CPU with FPGAs Glossary
Term Abbreviation Description
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Acceleration Stack

A collection of software, firmware, and tools that provides performance-optimized connectivity between an Intel® FPGA and an Intel® Xeon® processor.

Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) Intel® FPGA PAC

PCIe* FPGA accelerator card with Intel® FPGA PAC.

Contains a FPGA Interface Manager (FIM) that connects to an Intel® Xeon® processor over PCIe* bus.

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