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Ixiasoft
Visible to Intel only — GUID: mwh1409959489991
Ixiasoft
1.2. HDL Design Guidelines
Design style can affect logic utilization and timing performance, as well as the design’s reliability. This section describes basic design techniques that ensure optimal synthesis results for designs that target Intel FPGA devices while avoiding common causes of unreliability and instability. As a best practice, consider potential problems when designing combinational logic, and pay attention to clocking schemes so that the design maintains synchronous functionality and avoids timing issues.