AN 824: Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

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ID 683312
Date 8/08/2017
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Document Table of Contents
Document Table of Contents x
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide x
OpenCL BSP Compilation Flow OpenCL BSP Floorplan Partition Guidelines for OpenCL BSP Floorplanning Guidelines for Maximum Operating Frequency Guidelines for Evaluating BSP Resource Utilization Efficiency Document Revision History
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

The Intel® FPGA SDK for OpenCL™ Board Support Package (BSP) Floorplan Optimization Guide provides floorplanning guidelines for OpenCL™ 1 BSP. It also provides guidance on how you can acquire the base seed with best average maximum operating frequency and evaluate BSP resource utilization efficiency.

This document assumes that you are familiar with OpenCL 2 concepts as described in the OpenCL Specification version 1.0 by the Khronos Group.

1 The Intel® FPGA SDK for OpenCL™ is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
2 OpenCL and the OpenCL logo are trademarks of Apple Inc. and used by permission of the Khronos Group™.
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