AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.7. Step 7: Apply Plan Constraints

Follow these steps to apply the Interface Planner constraints to the FPGA_TOP project:
  1. In the Intel® Quartus® Prime Pro Edition software, close the FPGA_TOP project.
  2. Open a command shell and type the following command in the FGPA_TOP project directory. The Intel® Quartus® Prime Pro Edition executable must be in your PATH to run this command. 
    quartus_sh -t FPGA_TOP.pdp_assignments.tcl
  3. Reopen the FPGA_TOP project in the Intel® Quartus® Prime Pro Edition software. The project now contains the constraints that pdp_assignments.tcl defines.
  4. To run synthesis and apply the interface plan, click Analysis & Synthesis on the Compilation Dashboard.
  5. To run full compilation, click Compile Design on the Compilation Dashboard.
  6. Following compilation, click Assignments > Pin Planner to view placement results and complete the design floorplan.
    Figure 21. Full Design Floorplan in Pin Planner
By following the guidelines this application note describes, you can modify the FPGA_TOP design example to create a pinout that suits your systems and requirements.
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