AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.5. Step 5: Report Placement Data

You can generate Interface Planner placement and connectivity reports to help locate cells and make the best decisions about placement for the interfaces and elements in your design.

Follow these steps to access the placement reports

  1. Click the Reports tab. This tab displays a range of reports.
  2. In the Tasks list, click any report name to generate that report. The reports are interactive, allowing you select and Place, Unplace, or Report detailed data about the selected element.
  3. In the Flow control, click View Summary Report. The Interface Planner Summary lists details about IP block and periphery cell placement.
    Figure 18. Interface Planner Summary Report
  4. In the Tasks list, click Report All Placed Pins. The Placed Pins report shows that all IP have pin assignments.
    Figure 19. Report All Placed Pins
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