AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.3. Step 3: Update Plan with Project Assignments

Before planning the device periphery, you must reconcile any project assignments that Interface Planner imports, and run Update Plan to update the plan with these assignments.
  1. On the Flow control, click View Assignments (or click the Assignments tab). The Assignments tab displays the imported project assignments and notes any conflicts. At any time, click Plan > Reset Plan to reenable all project assignments.
    Figure 6.  Interface Planner Assignments Tab
  2. The Assignments tab displays the fixed pin locations for the transceiver reference clock pins on the left and right-hand side of the device. In a real planning session, you resolve any conflicts between assignments. You can easily filter the list by assignment name or status to enable or disable conflicting assignments.
  3. After resolving any assignment conflicts, click Update Plan on the Flow control. Interface Planner indicates when application of project assignments is complete.
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