AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.2. Step 2: Initialize Interface Planner

After synthesis is complete you can launch Interface Planner and initialize with synthesis results. Follow these steps to open the project in Interface Planner:
  1. Click Tools > Interface Planner (or click the Interface Planner button). The Interface Planner launches and displays a Welcome page and the Home tab.
  2. On the Flow control, click Initialize Interface Planner. This command starts background Fitter validation of your planning, and imports any existing assignments from the project. After initialization is complete, the Fitter dynamically validates your interface plan as you make changes in Interface Planner.
    Figure 5. Initialize Interface Planner
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