AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.1. Step 1: Project Setup

The FPGA_TOP project is ready to use with this application note. However, in a real design scenario, you must perform some initial project setup before using Interface Planner.

Interface Planner requires at least a partially complete, synthesized Intel® Quartus® Prime Pro Edition project as input. You can also use Interface Planner to place a fully complete design project. Before planning in Interface Planner, you must typically prepare the project in the following ways. These steps are already complete for the FPGA_TOP project.

  • Fully define known device periphery interfaces.
  • Instantiate all known interface IP cores.
  • Declare all general purpose I/Os.
  • Define the I/O standard, voltage, drive strength, and slew rate for all general purpose I/Os.
  • Define the core clocking (optional, but recommended).
  • Connect all interfaces of the periphery IP to virtual pins or test logic. This technique creates loop backs on any interfaces in the shell design, helping to ensure that periphery interfaces persist after synthesis optimization.

Follow these steps to open and synthesize the FPGA_TOP example design:

  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the FPGA_TOP.qpf project file.
    Note: You can optionally change the target device to match a different PCB or your own design requirements, as Modifying the FPGA_TOP Design Example describes.
  2. To run synthesis and apply the interface plan, click Analysis & Synthesis on the Compilation Dashboard.
    Figure 4.  Interface Planner Button and Compilation Dashboard
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