AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.4.2. Changing the Target FPGA

By default the FPGA _TOP design example targets the 1SG280HU1F50E1VG Intel® Stratix® 10 device. You can change the target device to match your resource or performance requirements. When you change the target device, you must allow the Compiler to remove all fixed location assignments, and automatically regenerate any IP for the new device.

Follow these steps to change the target device for the design example:

  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the FPGA_TOP.qpf project file.
  2. Click Assignments > Device.
    Figure 22. Target Device Selection
  3. In the Available Devices list, select an Intel® Stratix® 10 device that meets your design and PCB requirements. Click Yes when a message confirms that changing the device removes any existing location assignments.
  4. If the Intel® Quartus® Prime Pro Edition software indicates that one or more Intel® FPGA IP core is now outdated, follow these steps to upgrade the IP:
    1. Click Assignments > Settings > IP Settings, and enable Always regenerate design files for IP cores. This option ensures that all IP is the latest version following compilation.
      Figure 23. IP Settings Dialog Box
    2. Click OK.
  5. When ready, compile the design for the new target device.
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