1.2.3. Supported Configurations
The design examples only support a limited set of JESD204B Intel® FPGA IP parameter configurations. The IP parameter editor allows you to generate a design example only if the parameter configurations matches the following table.
Note: If you are not able to generate a design example that fully matches your desired parameter settings, choose the closest allowable parameter values for generation. Modify the post-generated design parameters manually in the Quartus® Prime software to match your desire parameter settings. Refer to the JESD204B Intel® FPGA IP User Guide for more details on the rules and ranges that govern each IP and transport layer parameter. Refer to Customizing the Design Example for more information about customizing the design example.
L | M | F |
---|---|---|
1 | 1 | 2 |
1 | 1 | 3 |
1 | 1 | 4 |
1 | 1 | 8 |
1 | 2 | 3 |
1 | 2 | 4 |
1 | 2 | 8 |
1 | 4 | 8 |
2 | 1 | 1 |
2 | 1 | 2 |
2 | 1 | 3 |
2 | 1 | 4 |
2 | 1 | 8 |
2 | 2 | 2 |
2 | 2 | 3 |
2 | 2 | 4 |
2 | 2 | 8 |
2 | 4 | 3 |
2 | 4 | 4 |
2 | 4 | 8 |
2 | 8 | 8 |
4 | 1 | 1 |
4 | 1 | 2 |
4 | 1 | 3 |
4 | 1 | 4 |
4 | 2 | 1 |
4 | 2 | 2 |
4 | 2 | 3 |
4 | 2 | 4 |
4 | 2 | 8 |
4 | 4 | 2 |
4 | 4 | 3 |
4 | 4 | 4 |
4 | 4 | 8 |
4 | 8 | 3 |
4 | 8 | 4 |
4 | 8 | 8 |
4 | 16 | 8 |
6 | 1 | 1 |
6 | 3 | 1 |
8 | 1 | 1 |
8 | 1 | 2 |
8 | 2 | 1 |
8 | 2 | 2 |
8 | 2 | 3 |
8 | 2 | 4 |
8 | 2 | 8 |
8 | 4 | 1 |
8 | 4 | 2 |
8 | 4 | 3 |
8 | 4 | 4 |
8 | 4 | 8 |
8 | 8 | 2 |
8 | 8 | 3 |
8 | 8 | 4 |
8 | 8 | 8 |
8 | 16 | 3 |
8 | 16 | 4 |
8 | 16 | 8 |
8 | 32 | 8 |
JESD204B IP Parameters | Values |
---|---|
Wrapper Options | Both Base and PHY |
Data Path |
|
JESD204B Subclass | 1 |
Data Rate | Any valid value2 |
PCS Option |
|
Bonding Mode |
|
PLL/CDR Reference Clock Frequency | Any valid value |
Enable Bit Reversal and Byte Reversal | Any valid value |
Enable Transceiver Dynamic Reconfiguration | Any valid value |
L |
|
M |
|
Enable manual F configuration |
|
F |
|
N | Integer, range 12 – 16 |
N’ |
|
S | Any valid value |
K | Any valid value |
Enable Scramble (SCR) | Any valid value |
CS | Integer, range 0 – 3 |
CF | 0 |
High Density User Data Format (HD) |
|
Enable Error Code Correction (ECC_EN) | Any valid value |
2 Refer to JESD204B Intel® FPGA IP User Guide for more details on maximum and minimum data rates for your target device.
3 L=6 is only allowed when F=1
4 M=3 is only allowed for L=6