JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
ID
683298
Date
7/29/2024
Public
Visible to Intel only — GUID: cqp1468565653854
Ixiasoft
1.2.1. Features
This design example has the following key features:
- System Console using Tcl script control mechanism
- Synthesis and simulation flows
- Configurable transport layer and pattern generator and checker modules
- Power-on self test with the following configurable test patterns:
- Alternating
- Ramp
- PRBS
- Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
- Supports option for 3-wire SPI