ed_sim |
The folder that contains simulation testbench files. |
ed_sim/testbench/models |
The folder that contains the testbench and source files. |
ed_sim/testbench/setup_scripts |
The folder that contains the test flow setup scripts. |
ed_sim/testbench/pattern |
The folder that contains the source files for the pattern generator/checker. |
ed_sim/testbench/transport_layer |
The folder that contains the source files for the transport layer. |
ed_sim/testbench/aldec |
The folder that contains the test flow run scripts for Riviera-PRO* simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/xcelium |
The folder that contains the test flow run scripts for Xcelium* Parallel simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/mentor |
The folder that contains the test flow run scripts for ModelSim* or QuestaSim* simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/synopsys/vcs |
The folder that contains the test flow run scripts for VCS* simulator. Also serves as the working directory for the simulator. |
ed_sim/testbench/synopsys/vcsmx |
The folder that contains the test flow run scripts for VCS* MX simulator. Also serves as the working directory for the simulator. |
ed_synth |
The folder that contains design example synthesizable components. |
ed_synth/ip |
The folder that contains Platform Designer-instantiated IP modules. |
ed_synth/altjesd_ed_qsys_<data path> |
The folder that contains Platform Designer-generated modules from the altjesd_ed_qsys_<data path>.qsys system. |
ed_synth/altjesd_ss_<data path> |
The folder that contains Platform Designer-generated modules from the altjesd_ss_<data path>.qsys system. |
ed_synth/pattern |
The folder that contains the source files for the pattern generator/checker. |
ed_synth/transport_layer |
The folder that contains the source files for the transport layer. |
ed_synth/altera_jesd204_ed_<data path>.qpf ed_synth/altera_jesd204_ed_<data path>.qsf |
Quartus® Prime project and settings files. |
ed_synth/altjesd_ed_qsys_<data path>.qsys |
Platform Designer top level system. |
ed_synth/altjesd_ss_<data path>.qsys |
Platform Designer subsystem. |
ed_synth/altera_jesd204_ed_<data path>.sv |
Top level HDL source file. |
ed_synth/altera_jesd204_ed_<data path>.sdc |
Top level design constraints file. |
ed_synth/system_console |
The folder that contains all files necessary to run scripts in System Console (See Design Example Files for more details on folder content). |
*.v |
Miscellaneous source files |
ip_sim |
The folder that contains the simulation script to generate the JESD204B IP core Verilog/VHDL simulation model. |