Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 6/26/2023
Public

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Document Table of Contents

ENABLE_SV_STATIC_ASSERTIONS

Evaluate SystemVerilog assertions using parameters and constants during synthesis.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name ENABLE_SV_STATIC_ASSERTIONS <value>

Default Value

Off

Example

set_global_assignment -name ENABLE_SV_STATIC_ASSERTIONS ON