Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 10/02/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel® FPGA IP Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II and Nios® V Processors HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.3. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II and Nios® V Processors HAL Driver x
1.10.1. Mailbox Client HAL API 1.10.2. LibRSU HAL API
1.10.1. Mailbox Client HAL API x
1.10.1.1. Mailbox Client Driver API
1.10.2. LibRSU HAL API x
1.10.2.1. Configuration Parameter 1.10.2.2. Error Codes 1.10.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.10.2.4. Data Type 1.10.2.5. Functions 1.10.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.7. Enabling Cryptographic Services

The cryptographic offloading feature is available for Intel Agilex® 7 devices in Intel® Quartus® Prime Pro Edition software version 21.3 or later.

To enable this feature in the IP parameter editor, set Enable Crypto Service parameter to 1. When enabled, the Mailbox Client IP generates an 64-bit AXI manager interface that is used to pass data between the cryptographic fabric IP and user space memory.

For more information about the Cryptographic Services Mailbox Commands, refer to the Security Methodology for Intel® FPGAs and Structured ASICs User Guide. The Security Methodology for Intel® FPGAs and Structured ASICs User Guide document available on the Intel® Resource & Design Center contains detailed descriptions of the security features and technologies in Intel Programmable Solutions products to help you select the security features necessary to meet your security objectives. Contact Intel Support with reference number 14014613136 for access to the Security Methodology for Intel® FPGAs and Structured ASICs User Guide.

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