Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II and Nios® V Processors HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II and Nios® V Processors HAL Driver x
1.10.1. Mailbox Client HAL API 1.10.2. LibRSU HAL API
1.10.1. Mailbox Client HAL API x
1.10.1.1. Mailbox Client Driver API
1.10.2. LibRSU HAL API x
1.10.2.1. Configuration Parameter 1.10.2.2. Error Codes 1.10.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.10.2.4. Data Type 1.10.2.5. Functions 1.10.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.10.2.1. Configuration Parameter

The LibRSU HAL API configuration parameters are stored in Board Support Package (BSP) setting file. You can edit the configuration parameters through the BSP Driver tab. If they are not specified, the LibRSU HAL API uses the default value.

Table 25.  Configuration Parameter
Variable Default Value Description
rsu_protected_slot none Allows protection on a certain slot number. Only slots between 0 and 31 can be protected by this feature. By default, no slot is protected.
rsu_log_level 3 Allows customization on how much logging information is displayed. The valid inputs are 1,2 and 3. By default, the log level is set as 3 and all logging information is displayed.
enable_spt_checksum Disable Enables check and maintenance of the SPT checksum. By default, the SPT checksum feature is disabled.
enable_rsu Disable Enables the RSU functions. By default, it is disabled and the Mailbox Client Intel FPGA IP core performs without the RSU functions.

fpga_device

  • Stratix10
Disable Allows configuration targeting the selected Intel FPGA devices. By default, the configuration targets Intel® Agilex™ devices, thus the Intel® Stratix® 10 setting is disabled.
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