F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

3. IP Parameter Settings

You customize the IP core by specifying parameters in the IP parameter editor.
Figure 5. IP Parameter Editor
Table 8.  Parameter Settings: IP Tab
Parameter Supported Values Default Setting Description
CPRI General Options
CPRI Rate
  • 1.2288G (8b/10b)
  • 2.4376G (8b/10b)
  • 3.072G (8b/10b)
  • 4.9152G (8b/10b)
  • 6.144G (8b/10b)
  • 9.8304G (8b/10b)
  • 10.1376G (64b/66b)
  • 10.1376G

    (64b/66b)

  • 12.16512G (64b/66b)
  • 12.16512G (64b/66b) with RS-FEC
  • 24.33024G (64b/66b)
  • 24.33024G (64b/66b) with RS-FEC
 24.33024G (64b/66b) with RS-FEC Selects the CPRI data rate.

The hard RS-FEC block is included in the core if you select 10.1376, 12.1651, and 24.33024 Gbps (64b/66b) with the RS-FEC option.

Enable Reconfiguration to 8b/10b Datapath
  • On
  • Off
 Off Turn on this parameter if you plan to reconfigure the CPRI line rate of your channels from 64b/66b datapath rates to 8b/10b datapath rates at run-time.

If this option is not enabled, the CPRI IP core uses fewer resources, and you cannot change to 8b/10b datapath rates at run-time.
CPRI Core Options
System PLL Frequency
  • 805.664062 MHz
  • 830.078125 MHz
  • 903.125 MHz
 805.664062 MHz Select the System PLL frequency for your IP.
Enable CDR Clock Output
  • On
  • Off
 Off Turn on this parameter to enable CDR reference clock output.

o_cdr_divclk = refclk/N

Refer to the Required Clock Frequencies for exact values.

CPRI PMA Options
PMA Reference Frequency
  • 153.6 MHz
  • 184.32 MHz
  • 122.88 MHz
 184.32 MHz Reference clock frequency support:
  • For CPRI line rates that include 8b/10b soft PCS, use a reference clock of 153.6 MHz or 122.88 MHz.
  • For CPRI line rates that include 64b/66b hard PCS, use a reference clock of 184.32 MHz or 122.88 MHz.
Configuration, Debug, and Extension Option
Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface
  • On
  • Off
 Off When turned On, the F-Tile CPRI PHY Intel FPGA IP core includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the Datapath and PMA interface block. it can perform certain tests and debug functions through JTAG using the System Console. This option may require that you include a jtag_debug link in the system.

For parameters in the Example Design tab, refer to the device specific F-Tile CPRI PHY Intel FPGA IP Design Example User Guide.

For parameters in the Analog Parameters tab, refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

When the CPRI rate is 6.1440G and below, there are extra 3 analog parameters to configure:
  • RXEQ VGA Gain
  • RXEQ High Frequency Boost
  • RXEQ DFE Data Tap1
Figure 6. For CPRI Rates 9.8304G and Above
Figure 7. For CPRI Rates 6.1440G and Below

The default and recommended analog parameters values are shown in the table below:

Table 9.  Default and Recommended Analog Parameter Values
Parameter Value
FGT TXEQ Post Tap 1, 1.0 step size 0
FGT TXEQ Main Tap 1.0 step size 35
FGT TXEQ Pre Tap 1, 1.0 step size 5
FGT TXEQ Pre Tap 2, 1.0 step size 0
FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_2 (100 ohms)
Enable FGT RX AC Couple ENABLE
Enable FGT VSR mode
  • VSR_MODE_LOW_LOSS (for CPRI rate 24Gbps only)
  • VSR_MODE_DISABLE (shown error if it’s not selected for CPRI rate below 24Gbps)
RXEQ VGA Gain 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ High Frequency Boost 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ DFE Data Tap1 0 (Required only when CPRI rate is 6.1440Gbps and below)

In the Example Design tab, if you select Target Development Kit to be Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit, and you configure analog parameters other than the default and recommended values, you will see warnings to recommend you set to the default values.

Figure 8. Target Development Kit in the Example Design Tab
Figure 9. Warnings
Related Information
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