Viterbi IP Core User Guide

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ID 683280
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Viterbi IP Core 2. Viterbi IP Core Getting Started 3. Viterbi IP Core Functional Description A. Viterbi IP Core User Guide Document Archives 4. Document Revision History
1. About the Viterbi IP Core x
1.1. Intel® DSP IP Core Features 1.2. Viterbi IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Viterbi IP Core Release Information 1.6. Viterbi IP Core Performance and Resource Utilization
2. Viterbi IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Viterbi IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. Viterbi IP Core Functional Description x
3.1. Decoder 3.2. Convolutional Encoder 3.3. Trellis Coded Modulation 3.4. Viterbi IP Core Parameters 3.5. Viterbi IP Core Interfaces and Signals
3.3. Trellis Coded Modulation x
3.3.1. Half-Rate Convolutional Codes 3.3.2. Trellis Decoder 3.3.3. About Converting Received Signals 3.3.4. Trellis Termination 3.3.5. Trellis Initialization
3.4. Viterbi IP Core Parameters x
3.4.1. Architecture 3.4.2. Code Sets 3.4.3. Viterbi Parameters 3.4.4. Test Data
3.4.1. Architecture x
3.4.1.1. BER Estimator 3.4.1.2. Node Synchronization
3.4.3. Viterbi Parameters x
3.4.3.1. Soft Symbol Input 3.4.3.2. State Metrics 3.4.3.3. Throughput Calculator 3.4.3.4. Latency Calculator
3.4.4. Test Data x
3.4.4.1. External Puncturing
3.5. Viterbi IP Core Interfaces and Signals x
3.5.1. Avalon-ST Interfaces in DSP IP Cores 3.5.2. Global Signals 3.5.3. Avalon-ST Sink Signals 3.5.4. Avalon Source-ST Signals 3.5.5. Configuration Signals 3.5.6. Status Signals 3.5.7. Viterbi IP Core Timing Diagrams
1. About the Viterbi IP Core
2. Viterbi IP Core Getting Started
3. Viterbi IP Core Functional Description
A. Viterbi IP Core User Guide Document Archives
4. Document Revision History

3.5.5. Configuration Signals

Signal Name Description
ber_clear Reset for the BER counter. Only for the BER block option.
bm_init_state[(L-1):1] Specifies the state in which to initialize with the value from the bm_init_value[] bus. All other state metrics are set to zero. the IP core latches bm_init_state when sink_sop is asserted. Hybrid architecture only.
bm_init_value[(L-1):1]

Specifies the value of the metric that initializes the start state. All other metrics are set to 0. bm_init_value must be larger than (L × 2(softbits – 1)). the IP core latches bm_init_value when sink_sop is asserted. Hybrid architecture only.

sel_code[log2(Ncodes):1] Selects the codeword. ’0’ selects the first codeword, ‘1’ selects the second, and so on. The bus size increases according to the number of codes specified. The IP core latches sel_code when sink_sop is asserted.
state_node_sync[log2(Nmax):1]

Specifies the node synchronization rotation to rr.

The IP core latches state_node_sync signal when sink_sop is asserted. Available only when you turn on Node Sync.

tb_length[] Traceback length. The maximum width of tb_length is equal to the maximum value of parameter v. The IP core latches tb_length input when sink_sop is asserted. This IP core disables this signal if you select the continuous optimization: you must then remove it from the testbench. Not available for parallel architectures with block optimization.
tb_type Parallel architectures only. Altera recommends that you set tb_type high always for future compatibility. In block decoding when tb_type is low, the decoder starts from state 0; when tb_type is high, the decoder uses the state specified in tr_init_state[(L-1):1]. For block decoding set tb_type high. The IP core latches tb_type when sink_eop is asserted. If you select None or Continuous optimization, the IP core connects this input to zero.
tr_init_state[(L-1):1] Specifies the state to start the traceback from, when tb_type is asserted high. The IP core latches tr_init_state when sink_eop is asserted. If you select continuous optimization, this input is removed from the top level design and connected to zero in the inner core.
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