Viterbi IP Core User Guide

ID 683280
Date 11/06/2017
Public
Document Table of Contents

3.4.3.4. Latency Calculator

The latency calculator gives you an approximate indication of the latency of your Viterbi decoder.

Latency is the number of clock cycles it takes the decoder to process r the data and output it. Latency is from the first symbol to enter the IP core (sink_sop) up to the first symbol to leave (source_sop). The latency depends on the parameters. For the precise latency, perform simulation. The latency calculator uses the following formula for the hybrid architecture:

Number of clock cycles = Z × V

where:

    • V is the traceback length value that is in the input tb_length
    • Z = 10, if log2C = 3
    • Z = 2log2C, if log2C > 3
    • log2C = L MAX – 2 – log2A, where A is ACS units

For the parallel architecture the number of clock cycles is approximately 4V.