AN 485: Serial Peripheral Interface Master in Altera MAX Series

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ID 683277
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Serial Peripheral Interface Master in Altera MAX Series
1. Serial Peripheral Interface Master in Altera MAX Series x
1.1. Using SPI Master in Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. Using SPI Master in Altera Devices x
1.1.1. SPI Interface 1.1.2. Host Interface
1.2. Implementation x
1.2.1. Source Code
1. Serial Peripheral Interface Master in Altera MAX Series

1.1. Using SPI Master in Altera Devices

Figure 1. Implementing an SPI Master using Supported Altera DevicesThis figure shows the host interfacing ports and SPI slave interfacing ports. The host processor controls the CPLD with the signals.

Section Content
SPI Interface
Host Interface

Level Two Title