AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

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ID 683275
Date 9/10/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G Wireless Acceleration Reference Design 2. 5G User Image Description 3. Document Revision History for AN 907: Enabling 5G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000
1. About the 5G Wireless Acceleration Reference Design x
1.1. 5G User Image Features 1.2. About the Intel PAC N3000
1.2. About the Intel PAC N3000 x
1.2.1. Factory Image for 2x2x25 GbE
2. 5G User Image Description x
2.1. User Image Power Management 2.2. 5G Channel Coder 2.3. Fronthaul IO 2.4. User Image Software
2.2. 5G Channel Coder x
2.2.1. 5G Channel Coder Throughput 2.2.2. 5G LDPC-V Transmitter and Receiver Test Cases 2.2.3. 5G VRAN Universal Verification Methodology
1. About the 5G Wireless Acceleration Reference Design
2. 5G User Image Description
3. Document Revision History for AN 907: Enabling 5G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000

2.2.3. 5G VRAN Universal Verification Methodology

The vRAN universal verification methodology (UVM) simulation test environment for the 5G channel coder incorporates the transmitter or receiver and the DMA subsystem. The test environment does not include the preverified transaction layer packet (TLP) adapter.

The tests randomly select 2,000 test patterns from 110,000 test patterns to test the decoding function and randomly selects 2,000 test patterns from 110,000 test patterns to test the encoding function. The tests also test the randomization (and functional coverage) of system scenarios such as HARQ, physical and virtual function (PF and VF) access, queue flushing, and reset. The reference design includes the UVM test plan, 5G_LDPC_Test_Plan.xls.

Figure 11. UVM Tests
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