External Memory Interfaces Arria® 10 FPGA IP Core Release Notes

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ID 683274
Date 4/01/2024
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1. External Memory Interfaces Arria® 10 FPGA IP Core Release Notes
1. External Memory Interfaces Arria® 10 FPGA IP Core Release Notes x
1.1. External Memory Interfaces Arria® 10 FPGA IP Core v19.2.3 1.2. External Memory Interfaces Arria® 10 FPGA IP Core v19.1.0 1.3. External Memory Interfaces Arria® 10 FPGA IP 19.1 1.4. External Memory Interfaces Arria® 10 FPGA IP 18.1 1.5. External Memory Interfaces Arria® 10 FPGA IP 18.0 1.6. Arria® 10 External Memory Interface IP 17.1 1.7. Arria 10 External Memory Interface IP 17.0 1.8. Arria 10 External Memory Interface IP 16.1
1. External Memory Interfaces Arria® 10 FPGA IP Core Release Notes

1.8. Arria 10 External Memory Interface IP 16.1

Table 8.  v16.1 November 2016
Description Impact
Implemented fix to address hardware calibration problems with DDR4 LRDIMM interfaces. (This change is a final bit-settings change for 10AX115 devices.) To incorporate this fix in existing DDR4 LRDIMM designs, regenerate the DDR4 IP and recompile the design.
Modified parameter editor for DDR4 RDIMM and LRDIMM to accept individual RDIMM/LRDIMM SPD data directly, without manual encoding. The IP then calculates the encoded RCD and DB configuration settings. If you are upgrading from a previous version that uses the encoded values, those values are still accepted by the new version of the IP.
DDR3 LRDIMM usage is currently restricted. If you select LRDIMM, you will not be able to generate an external memory interface IP for DDR3. Cannot generate EMIF IP for DDR3 LRDIMM. Contact Intel for support.
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