Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 11/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
2. Block-Based Design Flows x
2.1. Block-Based Design Terminology 2.2. Block-Based Design Overview 2.3. Design Methodologies Overview 2.4. Design Partitioning 2.5. Design Block Reuse Flows 2.6. Incremental Block-Based Compilation Flow 2.7. Setting-Up Team-Based Designs 2.8. Bottom-Up Design Considerations 2.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 2.10. Block-Based Design Flows Revision History 2.11. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
2.2. Block-Based Design Overview x
2.2.1. Design Block Reuse Overview 2.2.2. Incremental Block-Based Compilation Overview
2.2.1. Design Block Reuse Overview x
2.2.1.1. Design Block Reuse Examples
2.3. Design Methodologies Overview x
2.3.1. Top-Down Design Methodology Overview 2.3.2. Bottom-Up Design Methodology Overview 2.3.3. Team-Based Design Methodology Overview
2.4. Design Partitioning x
2.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 2.4.2. Creating Design Partitions 2.4.3. Design Partition Guidelines
2.5. Design Block Reuse Flows x
2.5.1. Reusing Core Partitions 2.5.2. Reusing Root Partitions 2.5.3. Reserved Core Entity Re-Binding 2.5.4. Viewing Quartus Database File Information
2.5.1. Reusing Core Partitions x
2.5.1.1. Step 1: Developer: Create a Design Partition 2.5.1.2. Step 2: Developer: Compile and Export the Core Partition 2.5.1.3. Step 3: Developer: Create a Black Box File 2.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
2.5.2. Reusing Root Partitions x
2.5.2.1. Step 1: Developer: Create a Reserved Core Partition 2.5.2.2. Step 2: Developer: Define a Logic Lock Region 2.5.2.3. Step 3: Developer: Compile and Export the Root Partition 2.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
2.5.4. Viewing Quartus Database File Information x
2.5.4.1. QDB File Attribute Types
2.6. Incremental Block-Based Compilation Flow x
2.6.1. Design Abstraction
2.6.1. Design Abstraction x
2.6.1.1. Empty Partition Clock Source Preservation
2.7. Setting-Up Team-Based Designs x
2.7.1. Creating a Top-Level Project for a Team-Based Design
2.7.1. Creating a Top-Level Project for a Team-Based Design x
2.7.1.1. Prepare a Design Partition for Project Integration
1. Answers to Top FAQs
2. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

2.5.1.4. Step 4: Consumer: Add the Core Partition and Compile

To add the core partition, the Consumer adds the black box as a source file in the Consumer project. After design elaboration, the Consumer defines a core partition and assigns the exported .qdb file to an instance in the Design Partitions Window. Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device family, and use the same Intel® Quartus® Prime software version, as the Developer project. The Consumer must supply a clock and any other constraints required for the interface to the core partition.
To add the core partition and compile the Consumer project:
  1. Create or open the Intel® Quartus® Prime project that you want to reuse the core partition.
  2. To add one or more black box files to the consumer project, click Project > Add/Remove Files in Project and select the black box file.
  3. Follow the steps in Creating Design Partitions to elaborate the design and define a core partition for the black box file. When defining the design partition, click the Partition Database File option and select the exported .qdb file for the core partition.
  4. To run all compilation stages through Fitter (Finalize) and generate the final snapshot, click Processing > Start > Start Fitter.
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