Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes

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ID 683245
Date 10/31/2016
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1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes
1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes x
1.1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v16.0 Revision History 1.2. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.1 Revision History 1.3. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History 1.4. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0 Revision History 1.5. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.1 Revision History 1.6. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.0 Revision History 1.7. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v13.1 Revision History
1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes

1.2. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.1 Revision History

Table 3.  v15.1 November 2015
Description Impact
Verified in Quartus Prime software v15.1 -
Made the following changes:
  • Changed the descriptions for tx_serial_clk_1g and rx_cdr_refclk_1g.
  • Added bit 12 to the 0x4B0 word address.
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Table 4.  10GBASE-KR IP Core Register Definition Changes v15.1Register definitions added or modified in version 15.1 for word address 0x4B0.
Bit RW Old Register Name New Register Name Description
12 RW N/A LT failure response When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY will restart LT.
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