Visible to Intel only — GUID: mwh1410383766671
Ixiasoft
Visible to Intel only — GUID: mwh1410383766671
Ixiasoft
2.4.4.4. Multicycle Paths
For hold time analysis, the timing analyzer analyzes the path for two timing conditions for every possible setup relationship, not just the worst-case setup relationship. Therefore, the hold launch and latch times can be unrelated to the setup launch and latch edges.
A multicycle constraint adjusts this default setup or hold relationship by the number of clock cycles you specify, based on the source (-start) or destination (-end) clock. A setup multicycle constraint of 2 extends the worst-case setup latch edge by one destination clock period. If you do not specify -start and -end values, the default constraint is -end.
Hold multicycle constraints derive from the default hold position (the default value is 0). An end hold multicycle constraint of 1 effectively subtracts one destination clock period from the default hold latch edge.
When the objects are timing nodes, the multicycle constraint only applies to the path between the two nodes. When an object is a clock, the multicycle constraint applies to all paths where the source node (-from) or destination node (-to) is clocked by the clock. When you adjust a setup relationship with a multicycle constraint, the default hold relationship adjusts automatically.
You can use timing constraints to modify either the launch or latch edge times that the Timing Analyzer uses to determine a setup relationship or hold relationship.
Command | Modification |
---|---|
set_multicycle_path -setup -end <value> | Latch edge time of the setup relationship. |
set_multicycle_path -setup -start<value> | Launch edge time of the setup relationship. |
set_multicycle_path -hold -end <value> | Latch edge time of the hold relationship. |
set_multicycle_path -hold -start <value> | Launch edge time of the hold relationship. |
Verify correct implementation of timing exception assignments by using the Report Exceptions (report_exceptions) command to report all exceptions to default timing analysis conditions.
Section Content
Common Multicycle Applications
Relaxing Setup with Multicycle (set_multicyle_path)
Accounting for a Phase Shift (-phase)