Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

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ID 683243
Date 8/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Timing Analysis Introduction 3. Using the Intel® Quartus® Prime Timing Analyzer A. Intel® Quartus® Prime Pro Edition User Guides
2. Timing Analysis Introduction x
2.1. What's New In This Version 2.2. Timing Analysis Basic Concepts 2.3. Timing Analysis Overview Document Revision History
2.2. Timing Analysis Basic Concepts x
2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
2.2.1. Timing Path and Clock Analysis x
2.2.1.1. The Timing Netlist 2.2.1.2. Timing Paths 2.2.1.3. Data and Clock Arrival Times 2.2.1.4. Launch and Latch Edges
2.2.5. Multicycle Path Analysis x
2.2.5.1. Multicycle Clock Hold 2.2.5.2. Multicycle Clock Setup
2.2.10. Time Borrowing x
2.2.10.1. Time Borrowing Limitations 2.2.10.2. Time Borrowing with Latches
3. Using the Intel® Quartus® Prime Timing Analyzer x
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
3.4. Step 3: Run the Timing Analyzer x
3.4.1. Setting the Operating Conditions for Timing Analysis 3.4.2. Enabling Time Borrowing Optimization 3.4.3. Promoting Critical Warnings to Errors
3.5. Step 4: Analyze Timing Reports x
3.5.1. Generating Timing Reports 3.5.2. Cross-Probing with Design Assistant 3.5.3. Launching Design Assistant from Timing Analyzer 3.5.4. Locating Timing Paths in Other Tools 3.5.5. Correlating Constraints to the Timing Report
3.5.1. Generating Timing Reports x
3.5.1.1. Report Fmax Summary 3.5.1.2. Report Timing 3.5.1.3. Report Timing By Source Files 3.5.1.4. Report Data Delay 3.5.1.5. Report Net Delay 3.5.1.6. Report Clocks and Clock Network 3.5.1.7. Report Clock Transfers 3.5.1.8. Report Metastability 3.5.1.9. Report CDC Viewer 3.5.1.10. Report Asynchronous CDC 3.5.1.11. Report Logic Depth 3.5.1.12. Report Neighbor Paths 3.5.1.13. Report Register Spread 3.5.1.14. Report Route Net of Interest 3.5.1.15. Report Retiming Restrictions 3.5.1.16. Report Register Statistics 3.5.1.17. Report Pipelining Information 3.5.1.18. Report Time Borrowing Data 3.5.1.19. Report Exceptions and Exceptions Reachability 3.5.1.20. Report Bottlenecks
3.5.1.13. Report Register Spread x
3.5.1.13.1. Registers with High Timing Path Endpoint Tension 3.5.1.13.2. Registers with High Immediate Fan-Out Tension
3.5.1.20. Report Bottlenecks x
3.5.1.20.1. Specifying Custom Bottleneck Criteria
3.5.2. Cross-Probing with Design Assistant x
3.5.2.1. Cross-Probing from Design Assistant to Timing Analyzer
3.6. Applying Timing Constraints x
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
3.6.1. Recommended Initial SDC Constraints x
3.6.1.1. Create Clock (create_clock) 3.6.1.2. Derive PLL Clocks (derive_pll_clocks) 3.6.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 3.6.1.4. Set Clock Groups (set_clock_groups)
3.6.4. Using Entity-bound SDC Files x
3.6.4.1. Entity-bound Constraint Scope 3.6.4.2. Entity-bound Constraint Examples
3.6.5. Creating Clocks and Clock Constraints x
3.6.5.1. Creating Base Clocks 3.6.5.2. Creating Virtual Clocks 3.6.5.3. Creating Generated Clocks (create_generated_clock) 3.6.5.4. Deriving PLL Clocks 3.6.5.5. Creating Clock Groups (set_clock_groups) 3.6.5.6. Accounting for Clock Effect Characteristics 3.6.5.7. Constraining CDC Paths
3.6.5.1. Creating Base Clocks x
3.6.5.1.1. Automatic Clock Detection and Constraint Creation
3.6.5.2. Creating Virtual Clocks x
3.6.5.2.1. Specifying I/O Interface Uncertainty 3.6.5.2.2. I/O Interface Clock Uncertainty Example
3.6.5.3. Creating Generated Clocks (create_generated_clock) x
3.6.5.3.1. Clock Divider Example (-divide_by) 3.6.5.3.2. Clock Multiplexer Example
3.6.5.5. Creating Clock Groups (set_clock_groups) x
3.6.5.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 3.6.5.5.2. Asynchronous Clock Groups (-asynchronous) 3.6.5.5.3. set_clock_groups Constraint Tips
3.6.5.6. Accounting for Clock Effect Characteristics x
3.6.5.6.1. Set Clock Latency (set_clock_latency) 3.6.5.6.2. Clock Uncertainty
3.6.6. Creating I/O Constraints x
3.6.6.1. Input Constraints (set_input_delay) 3.6.6.2. Output Constraints (set_output_delay)
3.6.7. Creating Delay and Skew Constraints x
3.6.7.1. Advanced I/O Timing and Board Trace Model Delay 3.6.7.2. Maximum Skew (set_max_skew) 3.6.7.3. Net Delay (set_net_delay)
3.6.8. Creating Timing Exceptions x
3.6.8.1. Timing Exception Precedence 3.6.8.2. False Paths (set_false_path) 3.6.8.3. Minimum and Maximum Delays 3.6.8.4. Multicycle Paths 3.6.8.5. Multicycle Exception Examples 3.6.8.6. Delay Annotation 3.6.8.7. Constraining Design Partition Ports
3.6.8.4. Multicycle Paths x
3.6.8.4.1. Common Multicycle Applications 3.6.8.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 3.6.8.4.3. Accounting for a Phase Shift (-phase)
3.6.8.5. Multicycle Exception Examples x
3.6.8.5.1. Default Multicycle Analysis 3.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 3.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 3.6.8.5.4. Same Frequency Clocks with Destination Clock Offset 3.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 3.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 3.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 3.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
3.7. Timing Analyzer Tcl Commands x
3.7.1. The quartus_sta Executable 3.7.2. Collection Commands
3.7.2. Collection Commands x
3.7.2.1. Wildcard Characters 3.7.2.2. Adding and Removing Collection Items 3.7.2.3. Query of Collections 3.7.2.4. Using the get_pins Command
1. Answers to Top FAQs
2. Timing Analysis Introduction
3. Using the Intel® Quartus® Prime Timing Analyzer
A. Intel® Quartus® Prime Pro Edition User Guides

3.5. Step 4: Analyze Timing Reports

During analysis, the Timing Analyzer examines the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as positive slack or negative slack. Negative slack indicates a timing violation. Positive slack indicates that timing requirements are met.

The Timing Analyzer provides very fine-grained reporting and analysis capabilities to identify and correct violations along timing paths. Generate timing reports to view how to best optimize the critical paths in your design. If you modify, remove, or add constraints, re-run timing analysis. This iterative process helps resolve timing violations in your design.

Figure 43. Timing Analyzer Shows Failing Paths in Red


Reports that indicate failing timing performance appear in red text, and reports that pass appear in black text. A gold question mark icon indicates reports that are outdated due to SDC changes since generation. Regenerate these reports to show the latest data.

The following sections describe how to generate various timing reports for analysis.


Section Content
Generating Timing Reports
Cross-Probing with Design Assistant
Launching Design Assistant from Timing Analyzer
Locating Timing Paths in Other Tools
Correlating Constraints to the Timing Report

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