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1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.6. Agilex™ 7 Embedded Memory Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Agilex™ 7 Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. M20K Embedded Memory Block Input Clock Quality Requirement
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.4.5. Shift Register Ports and Parameters Setting
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1.1. Agilex™ 7 Embedded Memory Features
The Agilex™ 7 devices contain the following types of memory blocks: Embedded SRAM (eSRAM) blocks, M20K blocks, and memory logic array blocks (MLABs).
Memory Blocks | Description | Device Variant Support |
---|---|---|
eSRAM |
|
Available in select F- and I- Series devices only. |
M20K |
|
Available in all F-, I-, and M-Series devices. |
MLABs |
|
In Agilex™ 7 devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Agilex™ 7 devices provide one 32×20 simple dual-port SRAM block per MLAB.
The Agilex™ 7 embedded memory blocks support the following operation modes:
- Single-port
- Simple dual-port
- True dual-port
- Simple quad-port
- ROM
Features | eSRAM | M20K | MLAB |
---|---|---|---|
Maximum operating frequency | 750 MHz |
|
1 GHz |
Total RAM bits (including parity bits) | 18.432 Mb | 20,480 bits | 640 bits |
Byte enable | N/A | Supported | Supported |
Address clock enable (address stall) |
N/A | Supported (only in simple dual-port RAM mode) | Supported |
Simple dual-port mixed width | N/A | Supported | N/A |
FIFO buffer mixed width | N/A | Supported | N/A |
Memory Initialization File (.mif) | N/A | Supported | Supported |
Dual-clock mode | N/A | Supported (only in simple dual-port RAM mode) | Supported |
Full synchronous memory | Supported | Supported | Supported |
Asynchronous memory | N/A | N/A | Only for flow-through read memory operations |
Power-up state | N/A | Output ports are cleared |
|
Asynchronous/Synchronous Clears | N/A |
|
Output registers and output latches |
Write/read operation triggering | Rising clock edges | Rising clock edges | Rising clock edges |
Same-port read-during-write | N/A | Output ports set to New Data , Old Data, or Don't Care | Output ports set to Don't Care |
Mixed-port read-during-write | Write-forwarding feature
|
|
Output ports set to New Data, Old Data, or Don't Care |
Error Correction Code (ECC) support |
|
|
N/A |
Force-to-Zero | N/A | Supported | N/A |
Coherent read memory | N/A | Supported | N/A |
Freeze logic | N/A | Supported | N/A |
True dual port (TDP) dual clock emulator | N/A | Supported | N/A |