Agilex™ 7 Embedded Memory User Guide

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ID 683241
Date 12/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Embedded Memory Overview 2. Agilex™ 7 Embedded Memory Architecture and Features 3. Agilex™ 7 Embedded Memory Design Considerations 4. Agilex™ 7 Embedded Memory IP References 5. Agilex™ 7 Embedded Memory Debugging 6. Agilex™ 7 Embedded Memory User Guide Archives 7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
1. Agilex™ 7 Embedded Memory Overview x
1.1. Agilex™ 7 Embedded Memory Features
2. Agilex™ 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks 2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Agilex™ 7 Embedded Memory Clocking Modes 2.7. Agilex™ 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Agilex™ 7 Supported Embedded Memory IPs
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Error Correction Code Truth Table 2.5.2. Parity Bit 2.5.3. ECC Parity Flip 2.5.4. ECC Read-During-Write Behavior
2.6. Agilex™ 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
3. Agilex™ 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. M20K Embedded Memory Block Input Clock Quality Requirement 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 7 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. eSRAM Agilex™ FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Agilex™ FPGA IP x
4.2.1. Release Information for eSRAM Agilex™ FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Agilex™ FPGA IP Parameters 4.2.4. eSRAM Agilex™ FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) Intel® FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

Document Version Quartus® Prime Version Changes
2024.12.17 24.3 Removed rdaddress port from SCLR options in the RAM: 2-PORT Intel® FPGA IP Parameter Settings table.
2024.10.21 24.2 Updated the legal values for MLAB/M20K for What is the width of a byte for byte enables? parameter for Parameter Settings: Clks/Rd, Byte En in the RAM: 2-PORT Intel® FPGA IP Parameter Settings table.
2024.10.02 24.2 Updated Parameter Settings: Clks/Rd, Byte En to remove Dual clock: use separate clocks for A and B ports clocking method in the RAM: 2-PORT Intel® FPGA IP Parameter Settings table.
2024.07.08 24.2
  • Added Read-During-Write topic.
  • Updated the description for sclr and aclr ports in the Input and Output Ports Description table.
  • Updated the description for lpm_hint in the FIFO Parameters table.
  • Removed mentions of Agilex 7 in the following (editorial edits to the text only; no change in the technical information):
    • The description for wrreq port in the Input and Output Ports Description table.
    • The note in the FIFO Synchronous Clear and Asynchronous Clear Effect topic.
    • The footnote for Effects on the q output for normal output modes mode in the Asynchronous Clear in DCFIFO table.
    • The Different Input and Output Width topic.
    • The Guidelines for Embedded Memory ECC Feature topic.
    • The Reset Scheme topic.
2024.03.29 23.2
  • Updated the description for the Using the FIFO parameter editor method in Table Configuration Methods for clarity.
  • Changed DISABLE_EMBEDDED_TIMING_CONSTRAINT to DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT for lpm_hint parameter in the FIFO Parameter Settings.
2023.10.19 23.2
  • Updated Reduce Power Consumption topic:
    • Replaced mention of "unused embedded memory blocks" with "embedded memory blocks" in the third bullet point.
    • Added a new bullet point about reducing power consumption in design.
  • Updated Coherent Read Memory topic to replace the mention of "Wide simple dual-port" with "Simple dual-port with more than 20-bit wide data".
2023.07.20 23.2 Added M20K Embedded Memory Block Input Clock Quality Requirement topic.
2023.06.26 23.1
  • Added Consider Registering the Memory Output topic.
2023.04.10 23.1
  • Added information for Intel Agilex® 7 M-Series support.
    • Added a new table: Intel Agilex® 7™ Embedded Memory Features.
    • Added a new topic: Fabric Network-On-Chip (NoC) in Intel Agilex® 7 M-Series M20K Blocks.
  • Updated product family name to " Intel Agilex® 7".
  • Retitled the document from Intel® Agilex™ Embedded Memory User Guide to Intel Agilex® 7 Embedded Memory User Guide.
2022.12.02 22.3 Removed the simple quad-port mode note for Intel® Stratix® 10 in Intel Agilex Embedded Memory Features.
2022.11.08 22.3 Updated power-up value for MLAB memory type in Initial Power-Up Values of Embedded Memory Blocks table in Consider Power-Up State and Memory Initialization topic.
2022.09.26 22.3
  • Added Consider the Memory Depth Setting topic.
  • Updated the description for Same-Port Read-During-Write Mode and Mixed-Port Read-During-Write Mode.
2022.04.25 21.1 Updated the description for True Dual Port Dual Clock Emulator topic.
2021.09.20 21.1
  • Updated the following topics:
    • Read/Write Clock
    • Input/Output Clock
  • Updated the description for Dual clock: use separate ‘input’ and ‘output’ clocks in Tables: RAM: 1-PORT Intel® FPGA IP Parameter Settings and RAM: 2-PORT Intel® FPGA IP Parameter Settings.
  • Updated the description in Reset Scheme for clarity.
2021.06.11 21.1
  • Updated the Byte Enable in Intel® Agilex™ Embedded Memory Blocks to state that the byte width for the byte enable signal may differ depending on your selected memory block in the embedded memory IP parameter editors.
2021.03.29 21.1
  • Updated the Intel® Agilex™ Embedded Memory IP References to include information about inferring memory functions from HDL code.
  • Updated the following tables:
    • Mixed Port Read-During-Write Output Behaviors
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 4-PORT Intel® FPGA IP Parameter Settings
    • ROM: 1-PORT Intel® FPGA IP Parameter Settings
    • ROM: 2-PORT Intel® FPGA IP Parameter Settings
    • eSRAM Intel® Agilex™ FPGA IP Parameter Editor: General Tab
    • FIFO Intel® FPGA IP Parameter Settings
2021.01.08 20.4 Updated the data bits written in Table: Byte Enable Controls in ×40 Data Width (M20K).
2020.12.14 20.4
  • Added the Shift Register (RAM-based) Intel® FPGA IP section.
  • Added the Avoid Changing Clock Signals and Other Memory Signals Simultaneously topic to the Intel® Agilex™ Embedded Memory Design Considerations section.
  • Added eSRAM Intel® Agilex™ FPGA IP information in Table: Intel® Agilex™ Memory IPs.
  • Updated Figure: Mixed-Port Read-During-Write: New_a_old_b Mode.
  • Updated the On Chip Memory RAM and ROM Intel® FPGA IPs section.
  • Updated the descriptions for the following parameters in Table: RAM: 1-PORT Intel® FPGA IP Parameters:
    • Create an ‘aclr’ asynchronous clear for the registered ports
    • Create an ‘sclr’ synchronous clear for the registered ports
  • Updated the description for clock0 in Table: Interface Signals of the Intel® Agilex™ RAM and ROM Intel® FPGA IP Cores.
  • Updated the eSRAM Intel® Agilex™ FPGA IP chapter:
    • Updated Figure: eSRAM Channel.
    • Updated Table: eSRAM Intel® Agilex™ FPGA IP Release Information.
    • Updated the widths for p<port_number>_data and p<port_number>_q signals in Table:eSRAM Intel® Agilex™ FPGA IP Input and Output Signals.
  • Updated the FIFO Intel® FPGA IP chapter:
    • Updated the footnotes for aclr (synchronize with read clock) mode in Table: Asynchronous Clear in DCFIFO.
    • Updated the description in the Gray-Code Counter Transfer at the Clock Domain Crossing topic of the FIFO section.
2019.12.09 19.3
  • Updated the eSRAM System Features section.
  • Updated Table: eSRAM Intel® Agilex™ FPGA IP Core Parameter Editor: Port Tab:
    • Updated the description for How wide should the data bus be?.
    • Removed Enable Dynamic ECC Encoder and Decoder Bypass.
  • Updated the eSRAM Intel® Agilex™ FPGA IP Interface Signals section:
    • Updated the descriptions for p<port_number>_data and p<port_number>_q signals.
    • Removed p<port_number>_eccdecbypass and p<port_number>_eccencbypass.
2019.11.19 19.3
  • Updated Table: Mixed Port Read-During-Write Output Behaviors:
    • Updated the Output Data when Read-During-Write value of the constrained_dont_care and dont_care parameters from "New data" to "Don't care".
    • Added a footnote to state that the output data is "don't care" because the IP does not guarantee metastability for the output data when read-during-write.
  • Updated the FIFO Intel® FPGA IP section.
2019.10.25 19.3
  • Added Intel® Agilex™ Embedded Memory IP Core References chapter.
  • Added IP release information for:
    • RAM: 1-PORT Intel® FPGA IP version 19.2.0
    • RAM: 2-PORT Intel® FPGA IP version 19.2.0
    • RAM: 4-PORT Intel® FPGA IP version 19.2.0
    • ROM: 1-PORT Intel® FPGA IP version 19.2.0
    • ROM: 2-PORT Intel® FPGA IP version 19.2.0
    • eSRAM Intel® Agilex™ FPGA IP version 19.1.2
    • FIFO Intel® FPGA IP version 19.1
  • Added new Topics:
    • Intel® Agilex™ Supported Embedded Memory IP Cores
    • Timing/Power Optimization Feature in M20K Blocks
    • Avoid Providing Non-Deterministic Input
  • Updated the following topics:
    • Intel Agilex Embedded Memory Features
    • Force-to-Zero
    • Freeze Logic
    • True Dual Port Dual Clock Emulator
    • Mixed-Port Read-During-Write Mode
  • Updated the features for eSRAM memory blocks in Table: Intel Agilex Embedded Memory Features.
  • Updated the depth of the eSRAM memory blocks in Table: Supported Embedded Memory Block Configurations.
  • Updated the description for Don't Care output mode in Table: Output Modes for RAM in Mixed-Port Read-During-Write Mode.
  • Added eSRAM output register and power-up value in Table: Initial Power-Up Values of Embedded Memory Blocks.
Document Version Changes
2019.04.02 Initial release.
Level Two Title