Intel® Agilex™ Embedded Memory User Guide

Download PDF
ID 683241
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ Embedded Memory Overview 2. Intel® Agilex™ Embedded Memory Architecture and Features 3. Intel® Agilex™ Embedded Memory Design Considerations 4. Intel® Agilex™ Embedded Memory IP References 5. Intel® Agilex™ Embedded Memory Debugging 6. Intel® Agilex™ Embedded Memory User Guide Archives 7. Document Revision History for the Intel® Agilex™ Embedded Memory User Guide
1. Intel® Agilex™ Embedded Memory Overview x
1.1. Intel® Agilex™ Embedded Memory Features
2. Intel® Agilex™ Embedded Memory Architecture and Features x
2.1. Byte Enable in Intel® Agilex™ Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Intel® Agilex™ Embedded Memory Clocking Modes 2.6. Intel® Agilex™ Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks 2.13. Intel® Agilex™ Supported Embedded Memory IPs
2.1. Byte Enable in Intel® Agilex™ Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.5. Intel® Agilex™ Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Intel® Agilex™ Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
3. Intel® Agilex™ Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Intel® Quartus® Prime Software for Memory
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Intel® Agilex™ Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. eSRAM Intel® Agilex™ FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® Agilex™ FPGA IP x
4.2.1. Release Information for eSRAM Intel® Agilex™ FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® Agilex™ FPGA IP Parameters 4.2.4. eSRAM Intel® Agilex™ FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) Intel® FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Intel® Agilex™ Embedded Memory Overview
2. Intel® Agilex™ Embedded Memory Architecture and Features
3. Intel® Agilex™ Embedded Memory Design Considerations
4. Intel® Agilex™ Embedded Memory IP References
5. Intel® Agilex™ Embedded Memory Debugging
6. Intel® Agilex™ Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Agilex™ Embedded Memory User Guide

4.3.3.5. FIFO Parameter Settings

Table 39.  FIFO Parameters
Parameter Type Required Description
lpm_width Integer Yes Specifies the width of the data and q ports for the SCFIFO function and DCFIFO function. For the DCFIFO_MIXED_WIDTHS function, this parameter specifies only the width of the data port.
lpm_width_r 16 Integer Yes Specifies the width of the q port for the DCFIFO_MIXED_WIDTHS function.
lpm_widthu Integer Yes Specifies the width of the usedw port for the SCFIFO function, or the width of the rdusedw and wrusedw ports for the DCFIFO function. For the DCFIFO_MIXED_WIDTHS function, it only represents the width of the wrusedw port.
lpm_widthu_r 16 Integer Yes Specifies the width of the rdusedw port for the DCFIFO_MIXED_WIDTHS function.
lpm_numwords Integer Yes Specifies the depths of the FIFO you require. The value must be at least 4.

The value assigned must comply to the following equation:

2^LPM_WIDTHU
lpm_showahead String Yes Specifies whether the FIFO is in normal mode (OFF) or show-ahead mode (ON). For more details, refer to SCFIFO and DCFIFO Look-Ahead Mode section.

If you set the parameter to ON, you may reduce performance.

lpm_type String No Identifies the library of parameterized modules (LPM) entity name. The values are SCFIFO and DCFIFO.
lpm_hint String No

This is a legacy parameter that is used to set the following:

  1. Maximum depth. You can set the maximum depth desired with “MAXIMUM_DEPTH=<depth>”. Allow the Intel® Quartus® Prime software to automatically choose the maximum depth of the RAM used in SCFIFO by ignoring this parameter.
  2. RAM block type. You can select the RAM block type with “RAM_BLOCK_TYPE=<M20K|MLAB|AUTO>”. The default value is AUTO.
  3. Disable Embedded Timing Constraint. This is a compulsory parameter to be set for DCFIFO, which disables the legacy set_false_path that resides in FIFO Intel® FPGA IP. Add “DISABLE_EMBEDDED_TIMING_CONSTRAINT=TRUE” to lpm_hint for proper timing analysis on the synchronizer path within DCFIFO IP.

Options should be concatenated with a comma in between and enclosed with double quotations. For example:

lpm_hint = ”MAXIMUM_DEPTH=512, RAM_BLOCK_TYPE=M20K”

overflow_checking String No Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO Intel® FPGA IP core is full. The values are ON or OFF. If omitted, the default is ON.
underflow_checking String No Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO Intel® FPGA IP core is empty. The values are ON or OFF. If omitted, the default is ON.

Note that reading from an empty SCFIFO gives unpredictable results.

enable_ecc 17 String No Specifies whether to enable the error checking and correcting (ECC) feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. This option is only available using M20K memory block type.

The ECC is disabled by default.

delay_wrusedw 18

String No Specify the number of register stages that you want to internally add to the rdusedw or wrusedw port using the respective parameter.

The default value of 1 adds a single register stage to the output to improve its performance. Increasing the value of the parameter does not increase the maximum system speed. It only adds additional latency to the respective output port.

add_usedw_msb_bit 18 String No Increases the width of the rdusedw and wrusedw ports by one bit. By increasing the width, it prevents the FIFO Intel® FPGA IP core from rolling over to zero when it is full. The values are ON or OFF. If omitted, the default value is OFF.
rdsync_delaypipe 18

wrsync_delaypipe 18

Integer No Specify the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_delaypipe parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the clocks_are_synchronized parameter to FALSE.

The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target device.

The values of these parameters are internally reduced by two. Thus, the default value of 3 for these parameters corresponds to a single synchronization stage; a value of 4 results in two synchronization stages, and so on. Choose at least 4 (two synchronization stages) for metastability protection.

use_eab String No Specifies whether or not the FIFO Intel® FPGA IP core is constructed using the RAM blocks. The values are ON or OFF.

Setting this parameter value to OFF yields the FIFO Intel® FPGA IP core implemented in ALMs regardless of the type of the TriMatrix memory block type assigned to the ram_block_type parameter.

This parameter is enabled by default. FIFO will be implemented using RAM blocks specified in ram_block_type.

write_aclr_synch 18 String No Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the wrclk clock. Adding the circuit prevents the race condition between the wrreq and aclr ports that could corrupt the FIFO Intel® FPGA IP core.

The values are ON or OFF. If omitted, the default value is OFF.

read_aclr_synch 18 String No Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the rdclk clock. Adding the circuit prevents the race condition between the rdreq and aclr ports that could corrupt the FIFO Intel® FPGA IP core.

The values are ON or OFF. If omitted, the default value is OFF.

clocks_are_synchronized 18 String No Specifies whether or not the write and read clocks are synchronized which in turn determines the number of internal synchronization stages added for stable operation of the FIFO. The values are TRUE and FALSE. If omitted, the default value is FALSE. You must only set the parameter to TRUE if the write clock and the read clock are always synchronized and they are multiples of each other. Otherwise, set this to FALSE to avoid metastability problems.

If the clocks are not synchronized, set the parameter to FALSE, and use the rdsync_delaypipe and wrsync_delaypipe parameters to determine the number of synchronization stages required.

ram_block_type String No Specifies the target device’s Trimatrix Memory Block to be used. To get the proper implementation based on the RAM configuration that you set, allow the Intel® Quartus® Prime software to automatically choose the memory type by ignoring this parameter and set the use_eab parameter to ON. This gives the compiler the flexibility to place the memory function in any available memory resource based on the FIFO depth required. Types of RAM block type available; Auto (default), MLAB, M20K and M144K.
add_ram_output_register String No Specifies whether to register the q output. The values are ON and OFF. If omitted, the default value is OFF.
almost_full_value 19 Integer No Sets the threshold value for the almost_full port. When the number of words stored in the FIFO Intel® FPGA IP core is greater than or equal to this value, the almost_full port is asserted.
almost_empty_value 19 Integer No Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO Intel® FPGA IP core is less than this value, the almost_empty port is asserted.
allow_wrcycle_when_full 19 String No Allows you to combine read and write cycles to an already full SCFIFO, so that it remains full. The values are ON and OFF. If omitted, the default is OFF. Use only this parameter when the OVERFLOW_CHECKING parameter is set to ON.
intended_device_family String No Specifies the intended device that matches the device set in your Intel® Quartus® Prime project. Use only this parameter for functional simulation.
16 Only applicable for the DCFIFO_MIXED_WIDTHS function.
17 Not applicable for the DCFIFO_MIXED_WIDTHS function.
18 Only applicable for the DCFIFO function.
19 Only applicable for the SCFIFO function.
Level Two Title