O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 3/07/2025
Public

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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold 3.7. O-RAN IP Fragmentation 3.8. O-RAN IP U-Plane Packet Size
3.6. O-RAN IP Transmission and Reception Window Threshold x
3.6.1. O-RAN IP Examples for Transmission and Reception Window Thresholds
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

5. O-RAN Intel FPGA IP User Guide Archive

For the latest and previous versions of this document, refer to: O-RAN Intel FPGA IP User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

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