Stratix® 10 Hard Processor System Technical Reference Manual
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10.4.6. ECC Controller Interrupts
The ECC controller has the ability to generate single- and double-bit error interrupts to the System Manager.
The ECC controller interrupt mechanism involves the System Manager, generic interrupt controller (GIC) and the Arm* Cortex* -A53 MPCore. The following steps outline the interrupt generation process when interrupts have been enabled through the Error Interrupt Enable (ERRINTEN) register.
- The ECC controller generates an interrupt when an error occurs and notifies the System Manager.
- The System Manager updates its interrupt status register and sends the interrupt to the GIC.
- The GIC sends the interrupt to the MPU.
- The MPU services the interrupt and clears the interrupt in the ECC controller.
- The System Manager clears the interrupt to the GIC and the corresponding interrupt status bit.