AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

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ID 683219
Date 1/16/2014
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for 100 Gbps - CFP2 Interface
1. Design Guidelines for 100 Gbps - CFP2 Interface x
1.1. Stratix V GT Transceiver Channels 1.2. CFP2 Host Connector Assembly and Pinout 1.3. Stratix V GT to CFP2 Interface Layout Design 1.4. BGA Breakout Optimization 1.5. CFP2 Interface Optimization 1.6. Example Design Channel Performance 1.7. Document Revision History
1.3. Stratix V GT to CFP2 Interface Layout Design x
1.3.1. Board Stack Up Dimensions
1.6. Example Design Channel Performance x
1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design
1. Design Guidelines for 100 Gbps - CFP2 Interface

1.2. CFP2 Host Connector Assembly and Pinout

The CFP2 specification defines the mechanical connector requirements for the 104-pin CFP2 connector. The host connector assembly is composed of a female host connector, and a metal connector cover and cage for retention and electromagnetic shielding of the inserted CFP2 optical module.

Figure 3. CFP2 Host Connector Assembly for a 4x25G/28G Module Interface as Defined by the CFP2 Mechanical Specification


Note: This figure is courtesy of Yamaichi Electronics.
Figure 4.  CFP2 Host Connector Pinout for 4x25G/28G Module Interface as Defined by the CFP2 Mechanical Specification


Figure 5.  CFP2 Host Connector Layout Footprint The high-speed transceiver pins are identified in the following figure to show their position within the connector. Blue pins are the TX transceiver channels and red pins are the RX transceiver channels.


Level Two Title