O-RAN Intel® FPGA IP Design Example User Guide

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ID 683218
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Agilex™ 7 F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Linking Format .elf Programming File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

2.3. Operating the O-RAN IP Design Example

After you download the design example .sof file to an FPGA:
  1. For Stratix® 10 and Agilex™ 7 designs, program the nios_system.elf software into the FPGA. Refer to Generating and Downloading the Programming File.
  2. Change the directory to <variation name>/synthesis/quartus/hardware_test/ and find the relevant system console script: .
    • oran_agilex.tcl for Agilex™ 7 designs.
    • oran_a10.tcl for Arria® 10 designs
    • oran_s10.tcl for Stratix® 10 designs
  3. For E-tile, you must perform either an internal or external loopback command once first after programming the SOF file for proper transceiver calibration.
  4. Change the TEST_MODE variable value in flow.c for the testing condition:
    • 0 - for simulation only, serial loopback enable
    • 1 - serial loopback enable
    • 2 - serial loopback + calibration
    • 3 - calibration only
    Whenever you change flow.c, recompile and regenerate the Nios V software, then reprogram the design into the FPGA before reprogramming the Nios V software application.
  5. Test the design operation through the commands supported in the system console script. The system console script provides useful commands for reading statistics and features enabling in the design.
    Table 3.  System Console Script Commands
    Command Description
    link_init_int_lpbk Enable transmitter to receiver internal serial loopback within the transceiver and perform the transceiver calibration flow. Ethernet Hard Intel FPGA IP (E-tile) only.
    link_init_ext_lpbk Enable transmitter to receiver external loopback and perform the transceiver calibration flow. Ethernet Hard Intel FPGA IP (E-tile) only.
    loop_off Disable transmitter to receiver internal serial loopback. 25G Ethernet Stratix® 10 FPGA IP (H-tile) and Low Latency Ethernet 10G MAC IP ( Arria® 10) only.
    loop_on Enable transmitter to receiver internal serial loopback. 25G Ethernet Stratix® 10 FPGA IP (H-tile) and Low Latency Ethernet 10G MAC IP ( Arria® 10) only.
    dr_25g_to_10g_etile Switch the data rate of the Ethernet MAC from 25G to 10G. Use for E-tile devices.
    dr_10g_to_25g_etile Switch the data rate of the Ethernet MAC from 10G to 25G. Use for E-tile devices.
    traffic_gen_enable Resets the entire design system, enables the traffic generator and checker.
    chkmac_stats Displays the statistics for Ethernet MAC.
    ext_continuous_mode_en Resets the entire design system, enables the traffic generator to generate continuous traffic packets.
    dr_25g_to_10g_htile Switch the data rate of the Ethernet MAC from 25G to 10G. Use for H-tile device.
    dr_10g_to_25g_htile Switch the data rate of the Ethernet MAC from 10G to 25G. Use for H-tile device.
    traffic_gen_disable Disables the traffic generators and checkers, resets the entire design system.
    read_test_statistics Displays the error statistics for traffic generators and checkers.
    Figure 9. System Console Printout (Number of channels = 1) 
    Channel 0 EXT PTP TX SOP Count: 128
Channel 0 EXT PTP TX EOP Count: 128
Channel 0 EXT MISC TX SOP Count: 4678620
Channel 0 EXT MISC TX EOP Count: 4692270
Channel 0 EXT RX SOP Count: 4707383
Channel 0 EXT RX EOP Count: 4721099
Channel 0 EXT Checker Errors: 0
Channel 0 EXT Checker Error Counts: 0
Channel 0 EXT PTP Fingerprint Errors: 0
Channel 0 EXT PTP Fingerprint Error Counts: 0
Channel 0 TX C SOP Count: 31307046
Channel 0 TX C EOP Count: 31393627
Channel 0 RX C SOP Count: 31483538
Channel 0 RX C EOP Count: 31612072
Channel 0 C Checker Errors: 0
Channel 0 C Checker Error Counts: 0
Channel 0 TX U SOP Count: 17907031
Channel 0 TX U EOP Count: 17956870
Channel 0 RX U SOP Count: 18006336
Channel 0 RX U EOP Count: 18055157
Channel 0 U Checker Errors: 0
Channel 0 U Checker Error Counts: 0

 ==========================================================================================
            ETHERNET MAC STATISTICS FOR Channel 0 (Rx)     
 ==========================================================================================
Fragmented Frames                 		: 0 
Jabbered Frames                   		: 0 
Right Size with FCS Err Frames     		: 0 
Multicast data  Err Frames        		: 0 
Broadcast data Err  Frames        		: 0 
Unicast data Err  Frames         		: 0 
64 Byte Frames                    		: 128 
65 - 127 Byte Frames              		: 50812181 
128 - 255 Byte Frames             		: 5081233 
256 - 511 Byte Frames             		: 0 
512 - 1023 Byte Frames            		: 0 
1024 - 1518 Byte Frames           		: 0 
1519 - MAX Byte Frames            		: 0 
> MAX Byte Frames                 		: 0 
Multicast data  OK  Frame       	  	: 55893542 
Broadcast data OK   Frame        	 	: 0 
Unicast data OK   Frames          		: 0 
Multicast Control Frames          		: 0 
Broadcast Control Frames          		: 0 
Unicast Control Frames            		: 0 
Pause Control Frames              		: 0 
Payload Octets OK                 		: 3847414692 
Frame Octets OK                    		: 4873823428 
Rx Maximum Frame Length			: 1518 
Any Size with FCS Err Frame			: 0 
Multicast control  Err Frame     		: 0 
Broadcast control Err  Frame     		: 0 
Unicast control Err  Frames      		: 0 
Pause control Err  Frames			: 0 
Rx Frame Starts                  		: 55893544
    Figure 10. System Console (25G to 10G DR E-tile) 
    Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G

DR Successful 25G -> 10G


RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :16114  (KHZ)
RXCLK :16113  (KHZ)
 RX PHY Status Polling 

 Rx Frequency Lock Status		0x0000000f 

 Mac Clock in OK Condition? 	0x00000001 

 Rx Frame Error ?				0x00000000 

 Rx PHY Fully Aligned? 		0x00000001 

Polling RX PHY Channel 0

RX PHY Channel 0 is up and running!
    Figure 11. System Console Printout (25G to 10G DR H-tile) 
    Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G

DR Successful 25G -> 10G


RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :15625  (KHZ)
RXCLK :15625  (KHZ)
 RX PHY Status Polling 

 Rx Frequency Lock Status		0x00000001 

 Mac Clock in OK Condition? 	0x00000007 

 Rx Frame Error ?				0x00000000 

 Rx PHY Fully Aligned? 		0x00000001 

Polling RX PHY Channel 0

RX PHY Channel 0 is up and running!
    Figure 12. System Console Printout (10G to 25G DR E-tile) 
    Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G

DR Successful 10G -> 25G


RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :40283  (KHZ)
RXCLK :40283  (KHZ)
 RX PHY Status Polling 

 Rx Frequency Lock Status		0x0000000f 

 Mac Clock in OK Condition? 	0x00000001 

 Rx Frame Error ?				0x00000000 

 Rx PHY Fully Aligned? 		0x00000001 

Polling RX PHY Channel 0

RX PHY Channel 0 is up and running!
    Figure 13. System Console Printout (10G to 25G DR H-tile) 
    Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G

DR Successful 10G -> 25G


RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :39061  (KHZ)
RXCLK :39063  (KHZ)
 RX PHY Status Polling 

 Rx Frequency Lock Status		0x00000001 

 Mac Clock in OK Condition? 	0x00000007 

 Rx Frame Error ?				0x00000000 

 Rx PHY Fully Aligned? 		0x00000001 

Polling RX PHY Channel 0

RX PHY Channel 0 is up and running!

Section Content
Generating and Downloading the Linking Format .elf Programming File

Level Two Title