O-RAN Intel® FPGA IP Design Example User Guide

Download PDF
ID 683218
Date 4/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Intel Agilex® 7 F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Programming .elf File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.04 23.1 1.7.0
  • Updated the product family name to "Intel Agilex 7."
2023.02.20 22.1 1.7.0 Added Xcelium steps to Simulating the O-RAN IP Design Example for Intel Agilex F-Tile Devices
2022.06.20 22.1 1.7.0
  • Added support for Intel Agilex I-series Transceiver SoC Development Kit
  • Added Questa simulator instructions
  • Removed --use-quartus-top-names from Simulating the Design Example.
2021.09.14 21.2 1.5.1
  • Added new Number of channels parameter.
  • Added new System Console Printout figures.
  • Changed block diagram
  • Changed clk_ref description
  • Replaced Test generator and verifier Avalon memory-mapped register table
2021.06.30 21.1 1.4.0 Added support for Intel Agilex 10 devices.
2020.11.30 20.3 1.1.0 Initial release.
Level Two Title