MAX® 10 FPGA Design Guidelines

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ID 683196
Date 5/15/2024
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Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA Design Guidelines
1. MAX® 10 FPGA Design Guidelines x
1.1. MAX® 10 FPGA Design Guidelines 1.2. Before You Begin 1.3. Design Specifications 1.4. Device Selection 1.5. Board Design 1.6. I/O and Clock Planning 1.7. Design Entry 1.8. Design Implementation 1.9. Document Revision History for the MAX® 10 Device Design Guidelines
1.2. Before You Begin x
1.2.1. Read through the Device Overview of the FPGA 1.2.2. Estimate design requirements 1.2.3. Review available design tools 1.2.4. Review available IP
1.3. Design Specifications x
1.3.1. Create detailed design specifications 1.3.2. Create detailed functional verification or test plan 1.3.3. Select IP that affects system design, especially I/O interfaces 1.3.4. Ensure your board design supports the Intel® FPGA IP Evaluation Mode tethered mode 1.3.5. Review available system development tools
1.4. Device Selection x
1.4.1. Consider the available device variants 1.4.2. Estimate the required logic, memory, and multiplier density 1.4.3. Consider vertical device migration availability and requirements 1.4.4. Review resource utilization reports of similar designs 1.4.5. Reserve device resources for future development and debugging 1.4.6. Estimate the number of I/O pins that you require 1.4.7. Consider the I/O pins you need to reserve for debugging 1.4.8. Verify that the number of LVDS channels are enough 1.4.9. Verify the number of PLLs and clock routing resources 1.4.10. Determine the device speed grade that you require 1.4.11. Determine the number of images supported for the device
1.5. Board Design x
1.5.1. Early Board Design 1.5.2. Power Pin Connections 1.5.3. Configuration Pin Connections 1.5.4. General I/O Pin Connections
1.5.1. Early Board Design x
1.5.1.1. Select a configuration scheme 1.5.1.2. Ensure board support the required features: 1.5.1.3. Plan for the Auto-restart after configuration error option 1.5.1.4. Estimating configuration file size 1.5.1.5. Review available on-chip debugging tools 1.5.1.6. Consider the guidelines to plan for debugging tools 1.5.1.7. Use the Early Power Estimator (EPE) to estimate power supplies and cooling solution
1.5.2. Power Pin Connections x
1.5.2.1. Design the board for power-up 1.5.2.2. Review the list of required supply voltages and the power supply options 1.5.2.3. Ensure I/O power pin compatibility with I/O standards 1.5.2.4. Ensure correct power pin connections 1.5.2.5. Determine power rail sharing 1.5.2.6. Use power distribution network (PDN) tool to plan for power distribution and decoupling capacitor selection 1.5.2.7. Review the following guidelines for PLL board design
1.5.3. Configuration Pin Connections x
1.5.3.1. Verify configuration pin connections and pull-up or pull-down resistors are correct for your configuration schemes 1.5.3.2. Design configuration TCK pin using the same technique as in designing high-speed signal or system clock 1.5.3.3. Verify the JTAG pins are connected to a stable voltage level if not in use 1.5.3.4. Verify the JTAG pin connections to the download cable header 1.5.3.5. Review the following JTAG pin connections guidelines: 1.5.3.6. Ensure the download cable and JTAG pin voltages are compatible 1.5.3.7. Buffer the JTAG signal according to the following guidelines: 1.5.3.8. Ensure all devices in the chain are connected properly 1.5.3.9. Determine if you need to turn on device-wide output enable
1.5.4. General I/O Pin Connections x
1.5.4.1. Specify the state of unused I/O pins 1.5.4.2. Refer to the Board Design Resource Center 1.5.4.3. Design VREF pins to be noise free 1.5.4.4. Refer to the Board Design Guideline Solution Center 1.5.4.5. Verify I/O termination and impedance matching 1.5.4.6. Perform full board routing simulation using IBIS models 1.5.4.7. Configure board trace models for Quartus® Prime advanced timing analysis 1.5.4.8. Review your pin connections
1.6. I/O and Clock Planning x
1.6.1. Early Pin Planning and I/O Assignment Analysis 1.6.2. I/O Features and Pin Connections 1.6.3. Clock Planning 1.6.4. I/O Simultaneous Switching Noise
1.6.1. Early Pin Planning and I/O Assignment Analysis x
1.6.1.1. Verify pin locations early in the FPGA place-and-route software 1.6.1.2. Use the Quartus® Prime Pin Planner for I/O pin planning, assignments, and validation 1.6.1.3. Check I/O restrictions related to ADC usage
1.6.2. I/O Features and Pin Connections x
1.6.2.1. Determine if your system requires single-ended I/O signaling 1.6.2.2. Determine if your system requires voltage-referenced signaling 1.6.2.3. Determine if your system requires differential signaling 1.6.2.4. Select a suitable signaling type and I/O standard for each I/O pin 1.6.2.5. Verify that all output signals in each I/O bank are intended to drive out at the bank's assigned VCCIO voltage level 1.6.2.6. Verify that all voltage-referenced signals in each I/O bank are intended to use the bank's VREF voltage (for devices that support VREF pins) 1.6.2.7. Check the I/O bank support for LVDS features 1.6.2.8. Verify the usage of the VREF pins that are used as regular I/Os 1.6.2.9. Test pin connections with boundary-scan test 1.6.2.10. Use the UNIPHY IP core for each memory interface, and follow connection guidelines 1.6.2.11. Use dedicated DQ/DQS pins and DQ groups for memory interfaces 1.6.2.12. Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O 1.6.2.13. Review available device I/O features that can help I/O interfaces 1.6.2.14. Consider OCT features to save board space and verify that the required termination scheme is supported for all pin locations
1.6.3. Clock Planning x
1.6.3.1. Use the device PLLs for clock management 1.6.3.2. Ensure that you select the correct PLL feedback compensation mode 1.6.3.3. Check that the PLL offers the required number of clock outputs and use dedicated clock output pins 1.6.3.4. Use the clock control block for clock selection and power-down 1.6.3.5. Instantiate PLL with ADC
1.6.4. I/O Simultaneous Switching Noise x
1.6.4.1. Consider the following recommendations to mitigate I/O simultaneous switching noise: 1.6.4.2. Check on the pin connection guidelines for the ADC pins
1.7. Design Entry x
1.7.1. Use synchronous design practices 1.7.2. Consider the following recommendations to avoid clock signals problems: 1.7.3. Use IP cores with the parameter editor 1.7.4. Review the information on dynamic reconfiguration feature 1.7.5. Consider the Altera's recommended coding styles to achieve optimal synthesis results 1.7.6. Enable the chip-wide reset to clear all registers if required 1.7.7. Use device architecture-specific register control signals 1.7.8. Review recommended reset architecture 1.7.9. Review the synthesis options available in your synthesis tool 1.7.10. Consider resources available for register power-up and control signals 1.7.11. Consider Altera's recommendations for creating design partitions 1.7.12. Perform timing budgeting and resource balancing between partitions 1.7.13. Create a design floorplan for incremental compilation partitions
1.8. Design Implementation x
1.8.1. Synthesis and Compilation 1.8.2. Timing Optimization and Analysis 1.8.3. Formal Verification 1.8.4. Power Analysis and Optimization
1.8.1. Synthesis and Compilation x
1.8.1.1. Specify your synthesis tool and use correct supported version 1.8.1.2. Review resource utilization reports after compilation 1.8.1.3. Review all Quartus® Prime messages, especially warning or error messages 1.8.1.4. Consider using incremental compilation 1.8.1.5. Ensure parallel compilation is enabled 1.8.1.6. Use the Compilation Time Advisor
1.8.2. Timing Optimization and Analysis x
1.8.2.1. Ensure timing constraints are complete and accurate 1.8.2.2. Review the Timing Analyzer reports after compilation 1.8.2.3. Ensure that the I/O timings are not violated when data is provided to the FPGA 1.8.2.4. Perform Early Timing Estimation before running a full compilation 1.8.2.5. Consider the following recommendations for timing optimization and analysis assignment: 1.8.2.6. Perform functional simulation at the beginning of your design flow 1.8.2.7. Perform timing simulation to ensure your design works in targeted device 1.8.2.8. Specify your simulation tool and use correct supported version
1.8.3. Formal Verification x
1.8.3.1. Determine if you require formal verification for your design 1.8.3.2. Check for support and design limitations for formal verification 1.8.3.3. Specify your formal verification tool and use correct supported version
1.8.4. Power Analysis and Optimization x
1.8.4.1. Provide accurate typical signal activities to get accurate power analysis result 1.8.4.2. Specify the correct operating conditions for power analysis 1.8.4.3. Analyze power consumption and heat dissipation in the Power Analyzer 1.8.4.4. Review recommended design techniques and Quartus® Prime options to optimize power consumption 1.8.4.5. Consider using a faster speed grade device 1.8.4.6. Optimize the clock power management 1.8.4.7. Reduce the number of memory clocking events 1.8.4.8. Consider I/O power guidelines 1.8.4.9. Reduce design glitches through pipelining and retiming 1.8.4.10. Review the information on power-driven compilation and Power Optimization Advisor 1.8.4.11. Reduce power consumption with architectural optimization
1. MAX® 10 FPGA Design Guidelines

1.7.11. Consider Altera's recommendations for creating design partitions

Partitioning a design for an FPGA requires planning to ensure optimal results when the partitions are integrated and ensures that each partition is well placed, relative to other partitions in the device.

Follow Altera's recommendations for creating design partitions to improve the overall quality of results. For example, registering partition I/O boundaries keeps critical timing paths inside one partition that can be optimized independently. Plan your source code so that each design block is defined in a separate file. The software can automatically detect changes to each block separately.

Use hierarchy in your design to provide more flexibility when partitioning. Keep your design logic in the leaves of the hierarchy trees; that is, the top level of the hierarchy should have very little logic, and the lower-level design blocks contain the logic.

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