Intel® FPGA RTE for OpenCL™ Pro Edition: Getting Started Guide

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ID 683173
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide 2. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for 64-Bit Windows 3. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for x86_64 Linux Systems 4. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for Intel® ARMv7-A SoC FPGA A. Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide Archives B. Document Revision History of the Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide
1. Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide x
1.1. Prerequisites for the Intel® FPGA RTE for OpenCL™ Pro Edition 1.2. Contents of the Intel® FPGA RTE for OpenCL™ Pro Edition 1.3. RTE Utility 1.4. Overview of the Intel® FPGA RTE for OpenCL™ Pro Edition Setup Process
1.1. Prerequisites for the Intel® FPGA RTE for OpenCL™ Pro Edition x
1.1.1. GCC Requirement
1.3. RTE Utility x
1.3.1. Displaying the Software Version 1.3.2. Listing the Intel® FPGA RTE for OpenCL™ Utility Command Options 1.3.3. Managing an FPGA Board 1.3.4. Managing Host Application
2. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for 64-Bit Windows x
2.1. Downloading the Intel® FPGA RTE for OpenCL™ Pro Edition 2.2. Installing the Intel® FPGA RTE for OpenCL™ Pro Edition 2.3. Setting the Intel® FPGA RTE for OpenCL™ Pro Edition User Environment Variables 2.4. Verifying Software Installation 2.5. Installing an FPGA Board 2.6. Updating the Hardware Image on the FPGA 2.7. Executing an OpenCL Kernel on an FPGA 2.8. Uninstalling the Software 2.9. Uninstalling an FPGA Board
2.6. Updating the Hardware Image on the FPGA x
2.6.1. Querying the Device Name of Your FPGA Board 2.6.2. Programming the Flash Memory of an FPGA
2.7. Executing an OpenCL Kernel on an FPGA x
2.7.1. Building the Host Application 2.7.2. Running the Host Application 2.7.3. Output from Successful Kernel Execution
3. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for x86_64 Linux Systems x
3.1. Downloading the Intel® FPGA RTE for OpenCL™ Pro Edition 3.2. Installing the Intel® FPGA RTE for OpenCL™ Pro Edition 3.3. Verifying Software Installation 3.4. Installing an FPGA Board 3.5. Updating the Hardware Image on the FPGA 3.6. Executing an OpenCL Kernel on an FPGA 3.7. Uninstalling the Software 3.8. Uninstalling an FPGA Board
3.2. Installing the Intel® FPGA RTE for OpenCL™ Pro Edition x
3.2.1. Setting the Intel® FPGA RTE for OpenCL™ Pro Edition User Environment Variables
3.5. Updating the Hardware Image on the FPGA x
3.5.1. Querying the Device Name of Your FPGA Board 3.5.2. Programming the Flash Memory of an FPGA
3.6. Executing an OpenCL Kernel on an FPGA x
3.6.1. Building the Host Application 3.6.2. Running the Host Application 3.6.3. Output from Successful Kernel Execution
4. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for Intel® ARMv7-A SoC FPGA x
4.1. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for SoC FPGA on Windows 4.2. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for SoC FPGA on Linux
4.1. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for SoC FPGA on Windows x
4.1.1. Downloading the Intel® FPGA SDK for OpenCL and the SoC EDS 4.1.2. Installing the Intel® FPGA SDK for OpenCL Pro Edition for SoC FPGA 4.1.3. Installing the Intel® SoC FPGA Embedded Development Suite Pro Edition 4.1.4. Recompiling the Linux Kernel Driver 4.1.5. Installing the Intel FPGA RTE for OpenCL Pro Edition onto the SoC FPGA Board 4.1.6. Installing the Intel® Arria® 10 SoC Development Kit 4.1.7. Executing an OpenCL Kernel on an SoC FPGA 4.1.8. Uninstalling the Intel® FPGA RTE for OpenCL™
4.1.7. Executing an OpenCL Kernel on an SoC FPGA x
4.1.7.1. Building the Host Application 4.1.7.2. Running the Host Application
4.2. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for SoC FPGA on Linux x
4.2.1. Downloading the Intel® FPGA SDK for OpenCL™ and the SoC EDS 4.2.2. Installing the Intel® FPGA SDK for OpenCL Pro Edition for SoC FPGA 4.2.3. Installing the Intel® SoC FPGA Embedded Development Suite Pro Edition 4.2.4. Recompiling the Linux Kernel Driver 4.2.5. Installing the Intel FPGA RTE for OpenCL Pro Edition onto the SoC FPGA Board 4.2.6. Installing the Intel® Arria® 10 SoC Development Kit 4.2.7. Executing an OpenCL Kernel on an SoC FPGA 4.2.8. Uninstalling the Intel® FPGA RTE for OpenCL™
4.2.7. Executing an OpenCL Kernel on an SoC FPGA x
4.2.7.1. Building the Host Application 4.2.7.2. Running the Host Application
1. Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide
2. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for 64-Bit Windows
3. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for x86_64 Linux Systems
4. Getting Started with the Intel® FPGA RTE for OpenCL™ Pro Edition for Intel® ARMv7-A SoC FPGA
A. Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide Archives
B. Document Revision History of the Intel® FPGA RTE for OpenCL™ Pro Edition Getting Started Guide

3.5.2. Programming the Flash Memory of an FPGA

Configure the FPGA by loading the hardware image of an Intel® FPGA RTE for OpenCL™ design example into the flash memory of the device. When there is no power, the FPGA retains the hardware configuration file in the flash memory. When you power up the system, it configures the FPGA circuitry based on this hardware image in the flash memory. Therefore, it is imperative that an OpenCL-compatible hardware configuration file is loaded into the flash memory of your FPGA.

Preloading an OpenCL image into the flash memory is necessary for the proper functioning of many Custom Platforms. For example, most PCIe®-based boards require a valid OpenCL image in flash memory so that hardware on the board can use the image to configure the FPGA device when the host system powers up for the first time. If the FPGA is not configured with a valid OpenCL image, the system fails to enumerate the PCIe endpoint, or the driver does not function.

Before running any designs, ensure that the flash memory of your board has a valid OpenCL image that is compatible with the current OpenCL software version. Consult your board vendor's documentation for board-specific requirements.

CAUTION:
When you load the hardware configuration file into the flash memory of the FPGA, maintain system power for the entire loading process, which might take a few minutes. Also, do not launch any host code that calls OpenCL kernels or might otherwise communicate with the FPGA board.

To load your hardware configuration file into the flash memory of your FPGA board, perform the following tasks:

  1. Install any drivers or utilities that your Custom Platform requires.
  2. To load the hardware configuration file into the flash memory, invoke the aocl flash <device_name> <design_example_filename>.aocx command, where <device_name> refers to the acl number (e.g. acl0 to acl127) that corresponds to your FPGA device, and <design_example_filename>.aocx is the hardware configuration file you create from the <design_example_filename>.cl file in the example design package.

    For more information about compiling an aocx file, refer to Creating the FPGA Hardware Configuration File of an OpenCL Kernel in the Intel FPGA SDK for OpenCL Pro Edition: Getting Started Guide.

  3. Power down your device or computer and then power it up again.
    Power cycling ensures that the FPGA configuration device retrieves the hardware configuration file from the flash memory and configures it into the FPGA.
    Warning: Some Custom Platforms require you to power cycle the entire host system after programming the flash memory. For example, PCIe-based Custom Platforms might require a host system restart to re-enumerate the PCIe endpoint. Intel® recommends that you power cycle the complete host system after programming the flash memory.
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