Stratix V Hard IP for PCI Express IP Core Release Notes

Download PDF
ID 683165
Date 10/31/2016
Public
Document Table of Contents
Document Table of Contents x
1. Stratix V Hard IP for PCI Express IP Core Release Notes
1. Stratix V Hard IP for PCI Express IP Core Release Notes x
1.1. Stratix V Hard IP for PCI Express IP Core v16.1 1.2. Stratix V Hard IP for PCI Express IP Core v16.0 1.3. Stratix V Hard IP for PCI Express IP Core v15.0 1.4. Stratix V Hard IP for PCI Express IP Core v14.1 1.5. Stratix V Hard IP for PCI Express IP Core v14.0 1.6. Stratix V Hard IP for PCI Express IP Core v13.1
1. Stratix V Hard IP for PCI Express IP Core Release Notes

1.2. Stratix V Hard IP for PCI Express IP Core v16.0

Table 2.  v16.0 May 2016
Description Impact
For the V-Series Avalon® Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core, rearchitected the Write DMA module for the 128-bit interface to the Application Layer. Provides higher throughput for external memories.
For the V-Series Avalon-MM DMA for PCI Express IP Core, the 256-bit interface to the Application Layer now supports a maximum transfer size of 64 kilobytes (KB). Large transfers require fewer descriptor table entries.
For the Avalon Streaming (Avalon-ST) with Single Root I/O Virtualization (SR-IOV) variant, removed support for the 128-bit interface to the Application Layer. Beginning in Quartus® Prime 16.0, Altera recommends the 256-bit interface to the Application Layer for all new designs. If you have a mature design using the 128-bit interface, continue to use the 15.1 release. For designs in the early stages of development, Altera recommends that you move to the 16.0 software and the 256-bit interface.

For the Avalon-ST with SR-IOV variant, changed address map for the following registers:

  • SR-IOV Virtualization Extended Capabilities
  • ARI
  • Secondary PCI Express Extended Capability Header
 If you update to the Quartus® Prime 16.0 software, you must update your hardware and software to use the new register addresses.
Level Two Title