HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683156
Date 1/26/2024
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

2.13. Simulation Testbench

The simulation testbench simulates the HDMI TX serial loopback to the RX core.
Note: This simulation testbench is not supported for designs with the Include I2C parameter enabled.
Figure 19.  HDMI Intel® FPGA IP Simulation Testbench Block Diagram
Table 24.  Testbench Components
Component Description
Video TPG The video test pattern generator (TPG) provides the video stimulus.
Audio Sample Gen The audio sample generator provides audio sample stimulus. The generator generates an incrementing test data pattern to be transmitted through the audio channel.
Aux Sample Gen The aux sample generator provides the auxiliary sample stimulus. The generator generates a fixed data to be transmitted from the transmitter.
CRC Check This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate.
Audio Data Check The audio data check compares whether the incrementing test data pattern is received and decoded correctly.
Aux Data Check The aux data check compares whether the expected aux data is received and decoded correctly on the receiver side.

The HDMI simulation testbench does the following verification tests:

HDMI Feature Verification
Video data
  • The testbench implements CRC checking on the input and output video.
  • It checks the CRC value of the transmitted data against the CRC calculated in the received video data.
  • The testbench then performs the checking after detecting 4 stable V-SYNC signals from the receiver.
Auxiliary data
  • The aux sample generator generates a fixed data to be transmitted from the transmitter.
  • On the receiver side, the generator compares whether the expected auxiliary data is received and decoded correctly.
Audio data
  • The audio sample generator generates an incrementing test data pattern to be transmitted through the audio channel.
  • On the receiver side, the audio data checker checks and compares whether the incrementing test data pattern is received and decoded correctly.

A successful simulation ends with the following message:

# SYMBOLS_PER_CLOCK 	= 2
# VIC               	= 4
# FRL_RATE          	= 0
# BPP               	= 0
# AUDIO_FREQUENCY (kHz)  = 48
# AUDIO_CHANNEL     	= 8
# Simulation pass
Table 25.   HDMI Intel® FPGA IP Design Example Supported Simulators
Simulator Verilog HDL VHDL
ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition Yes Yes
VCS* / VCS* MX Yes Yes
Riviera-PRO* Yes Yes
Xcelium* Parallel Yes No
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