HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 7/29/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

3.3. Directory Structure

The directories contain the generated files for the HDMI Intel® FPGA IP design example.
Figure 22. Directory Structure for the Design Example
Table 29.  Generated RTL Files
Folders Files
gxb
  • /gxb_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_rx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx_reset.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_fpll.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_fpll.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_reset.ip ( Intel® Quartus® Prime Pro Edition)
hdmi_rx
  • /hdmi_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_rx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_rx_top.v
/mr_clock_sync.v ( Intel® Quartus® Prime Standard Edition)
/mr_hdmi_rx_core_top.v ( Intel® Quartus® Prime Standard Edition)
/mr_rx_oversample.v ( Intel® Quartus® Prime Standard Edition)
/symbol_aligner.v
Panasonic.hex ( Intel® Quartus® Prime Pro Edition)
hdmi_tx
  • /hdmi_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_tx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_tx_top.v
/mr_ce.v ( Intel® Quartus® Prime Standard Edition)
/mr_hdmi_tx_core_top.v ( Intel® Quartus® Prime Standard Edition)
/mr_tx_oversample.v ( Intel® Quartus® Prime Standard Edition)
i2c_master

( Intel® Quartus® Prime Standard Edition)

/i2c_master_bit_ctrl.v
/i2c_master_byte_ctrl.v
/i2c_master_defines.v
/i2c_master_top.v
/oc_i2c_master.v
/oc_i2c_master_hw.tcl
/timescale.v
i2c_slave /edid_ram.qsys ( Intel® Quartus® Prime Standard Edition)
/Panasonic.hex ( Intel® Quartus® Prime Standard Edition)
/i2c_avl_mst_intf_gen.v
/i2c_clk_cnt.v
/i2c_condt_det.v
/i2c_databuffer.v
/i2c_rxshifter.v
/i2c_slvfsm.v
/i2c_spksupp.v
/i2c_txout.v
/i2c_txshifter.v
/i2cslave_to_avlmm_bridge.v
pll
  • /pll_hdmi.qsys ( Intel® Quartus® Prime Standard Edition)
  • /pll_hdmi.ip ( Intel® Quartus® Prime Pro Edition)
  • /pll_hdmi_reconfig.qsys ( Intel® Quartus® Prime Standard Edition)
  • /pll_hdmi_reconfig.ip ( Intel® Quartus® Prime Pro Edition)
quartus.ini
common
  • /clock_control.qsys ( Intel® Quartus® Prime Standard Edition)
  • /clock_control.ip ( Intel® Quartus® Prime Pro Edition)
  • /fifo.qsys ( Intel® Quartus® Prime Standard Edition)
  • /fifo.ip ( Intel® Quartus® Prime Pro Edition)
  • /output_buf_i2c.qsys ( Intel® Quartus® Prime Standard Edition)
  • /output_buf_i2c.ip ( Intel® Quartus® Prime Pro Edition)
/reset_controller.qsys ( Intel® Quartus® Prime Standard Edition)
/clock_crosser.v
dcfifo_inst.v
debouncer.sv ( Intel® Quartus® Prime Pro Edition)
hdr /altera_hdmi_aux_hdr.v
/altera_hdmi_aux_snk.v
/altera_hdmi_aux_src.v
/altera_hdmi_hdr_infoframe.v
/avalon_st_mutiplexer.qsys
reconfig_mgmt /mr_compare_pll.v
/mr_compare_rx.v
/mr_rate_detect.v
/mr_reconfig_master_pll.v
/mr_reconfig_master_rx.v
/mr_reconfig_mgmt.v
/mr_rom_pll_dprioaddr.v
/mr_rom_pll_valuemask_8bpc.v
/mr_rom_pll_valuemask_10bpc.v
/mr_rom_pll_valuemask_12bpc.v
/mr_rom_pll_valuemask_16bpc.v
/mr_rom_rx_dprioaddr_bitmask.v
/mr_rom_rx_valuemask.v
/mr_state_machine.v
sdc /a10_hdmi2.sdc
/mr_reconfig_mgmt.sdc
/jtag.sdc
/rxtx_link.sdc
/mr_clock_sync.sdc ( Intel® Quartus® Prime Standard Edition)
Table 30.   Generated Simulation FilesRefer to the Simulation Testbench section for more information.
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
<cds_libs folder>
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
/vcsmx/synopsys_sim_setup
xcelium

( Intel® Quartus® Prime Pro Edition)

/cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
<cds_libs folder>
common

( Intel® Quartus® Prime Pro Edition)

/modelsim_files.tcl
/riviera_files.tcl
/vcs_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
hdmi_rx
  • /hdmi_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_rx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_rx.sopcinfo ( Intel® Quartus® Prime Standard Edition)
/Panasonic.hex ( Intel® Quartus® Prime Pro Edition)
/symbol_aligner.v ( Intel® Quartus® Prime Pro Edition)
hdmi_tx
  • /hdmi_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_tx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_tx.sopcinfo ( Intel® Quartus® Prime Standard Edition)
Table 31.  Generated Software Files
Folders Files
tx_control_src
Note: The tx_control folder also contains duplicates of these files.
/intel_fpga_i2c.c ( Intel® Quartus® Prime Pro Edition)
/intel_fpga_i2c.h ( Intel® Quartus® Prime Pro Edition)
/i2c.c ( Intel® Quartus® Prime Standard Edition)
/i2c.h ( Intel® Quartus® Prime Standard Edition)
/main.c
/xcvr_gpll_rcfg.c
/xcvr_gpll_rcfg.h
/ti_i2c.c ( Intel® Quartus® Prime Standard Edition)
/ti_i2c.h ( Intel® Quartus® Prime Standard Edition)
Level Two Title