Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

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ID 683147
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

2.1. Features

DUT features:

  • Standard CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
  • Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • RX CRC checking and error reporting.
  • TX error insertion capability to transmit error frame at the end of a packet cycle.
  • Hardware and software reset control.
Level Two Title