Supply Pins
(See Note 12)
Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| VCCINT | Power | These are internal logic array voltage supply pins. | All VCCINT pins must be connected to either a 1.0V supply or a 1.2 V supply. Intel® Cyclone® 10 LP devices with VCCINT 1.0V, and Intel® Cyclone® 10 LP devices with VCCINT 1.2V, have different ordering codes. See Note 15. You have the option to share VCCD_PLL with VCCINT with a proper isolation filter. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 4. |
| VCCD_PLL[1..4] | Power | Digital power for PLLs[1..4]. You must power up these pins, even if the PLL is not used. | You are required to connect these pins to either 1.0 V (if VCCINT 1.0 V) or 1.2 V (if VCCINT 1.2 V), even if the PLL is not used. Intel® Cyclone® 10 LP devices with VCCINT 1.0 V, and Intel® Cyclone® 10 LP devices with VCCINT 1.2 V, have different ordering codes. See Note 15. With a proper isolation filter, these pins can be sourced from the same regulator as VCCINT. Use an isolated switching power supply with ± 3% maximum voltage ripple. See Note 11. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 2, 4, and 6. |
| VCCA[1..4] | Power | Analog power for PLLs[1..4]. All VCCA pins must be powered and all VCCA pins must be powered up and powered down at the same time even if not all the PLLs are used. Designer is advised to keep this pin isolated from other VCC pins for better jitter performance. | You are required to connect these pins to 2.5 V, even if the PLL is not used. Use an isolated linear or switching power supply with ± 3% maximum voltage ripple. See Note 11. Intel® recommends you to keep this pin isolated from other VCC for better jitter performance. |
| VCCIO[1..8] | Power | These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the input and output buffers for all I/O standards. | Connect these pins to 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V supplies, depending on the I/O standard assigned to the I/O bank. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 4. |
| GND | Ground | Device ground pins. | All GND pins should be connected to the board GND plane. |
| GNDA[1..4] | Ground | Ground for PLLs[1..4] and other analog circuits in the device. | You can consider connecting the GNDA pins to the GND plane without isolating the analog ground plane on the board provided that the digital GND planes are stable, quiet, and with no ground bounce effect. |
| VREFB[1..8]N[0..2] | I/O | Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. | If VREF pins are not used, you should connect them to either the VCCIO in the bank in which the pin resides or GND. Decoupling depends on the design decoupling requirements of the specific board. See Note 2. |