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1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide
5.3.1. Insert Line
5.3.2. Insert/Check CRC
5.3.3. Insert Payload ID
5.3.4. Match TRS
5.3.5. Scrambler
5.3.6. TX Sample
5.3.7. Clock Enable Generator
5.3.8. RX Sample
5.3.9. Detect Video Standard
5.3.10. Detect 1 and 1/1.001 Rates
5.3.11. Transceiver Controller
5.3.12. Descrambler
5.3.13. TRS Aligner
5.3.14. 3Gb Demux
5.3.15. Extract Line
5.3.16. Extract Payload ID
5.3.17. Detect Format
5.3.18. Sync Streams
5.3.19. Convert SD Bits
5.3.20. Insert Sync Bits
5.3.21. Remove Sync Bits
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion
5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion
5.4.3. SMPTE RP168 Switching Support
5.4.4. SD 20-Bit Interface for Dual/Triple Rate
5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
5.4.6. Intel FPGA Video Streaming Interface
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core
7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel
7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates
7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel
7.1.2.5. Potential Routing Problem During Fitter Stage in Arria® 10 and Cyclone® 10 GX Devices
7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Arria® 10 and Cyclone® 10 GX Devices
7.1.2.7. Unused Transceiver Channels
7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Stratix® 10 Devices
7.1.3.1. System PLL Clocking Mode
7.1.3.2. RX Transceiver Settings
7.1.3.3. TX Transceiver Settings
7.1.3.4. Unused Transceiver Tiles
7.1.3.5. SmartVID Settings
DK-SI-AGI027FA and DK-SI-AGI027FC (Not Intel® Enpirion® )
DK-SI-AGI027FB and DK-SI-AGI027FES ( Intel® Enpirion® )
7.1.3.6. Dynamic Reconfiguration
7.1.3.7. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
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7.1.3.5. SmartVID Settings
Agilex™ 7 silicon assembled on this development kit enables SmartVID feature by default. In order to prevent the Quartus® Prime software from generating an error due to incomplete SmartVID settings, put the following constraints into the Quartus® Prime project QSF file. These constraints are designed for the Intel® Enpirion® ED8401 core circuit.
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62 set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
DK-SI-AGI027FA and DK-SI-AGI027FC (Not Intel® Enpirion® )
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
DK-SI-AGI027FB and DK-SI-AGI027FES ( Intel® Enpirion® )
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401 set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"