SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Public
Document Table of Contents

7.1.3.5. SmartVID Settings

Agilex™ 7 silicon assembled on this development kit enables SmartVID feature by default. In order to prevent the Quartus® Prime software from generating an error due to incomplete SmartVID settings, put the following constraints into the Quartus® Prime project QSF file. These constraints are designed for the Intel® Enpirion® ED8401 core circuit.

set_global_assignment -name USE_PWRMGT_SCL SDM_IO0

set_global_assignment -name USE_PWRMGT_SDA SDM_IO12

set_global_assignment -name USE_CONF_DONE SDM_IO16

set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62

set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"

set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"

set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"

set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1

set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS

DK-SI-AGI027FA and DK-SI-AGI027FC (Not Intel® Enpirion® )

set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888

set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"

DK-SI-AGI027FB and DK-SI-AGI027FES ( Intel® Enpirion® )

set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401

set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"