SDI II Intel® FPGA IP User Guide

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ID 683133
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices 7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Arria® 10 and Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Arria® 10 and Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Stratix® 10 Devices
7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. SmartVID Settings 7.1.3.6. Dynamic Reconfiguration 7.1.3.7. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

4. SDI II IP Core Parameters

Note: For SDI II design example parameters, refer to the respective SDI II design example user guides.
Table 12.   SDI II IP Core Parameters
Note: Transceiver Options are available only for Arria V, Cyclone V, and Stratix V devices.
Parameter Value Description
Configuration Options
Video standard SD-SDI, HD-SDI, 3G-SDI, HD-SDI dual link, Dual rate (up to HD-SDI), Triple rate (up to 3G-SDI), Multi rate (up to 12G-SDI) Sets the video standard.
  • SD-SDI—disables option for line insertion and extraction, and CRC generation and extraction
  • HD-SDI—enables option for in line insertion and extraction and CRC generation and extraction
  • Dual-, triple-, or multi-rate SDI—includes the processing blocks for the respective supported rates. Logics for bypass paths and to automatically switch between the input standards are included.
Note: SD-SDI, HD-SDI dual link, and dual-rate (up to HD-SDI) options are not available for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices. Multi-rate (up to 12G-SDI) option is not available for Arria V, Cyclone V and Stratix V devices.
Note: 12G-SDI single-rate which was available in Agilex™ 7 device family in Quartus 21.4 is replaced by multi-rate (up to 12G) mode. The IP with multi-rate mode must be regenerated.
SD interface bit width 10, 20 Selects the SD interface bit width. Only applicable for dual rate and triple rate.
Direction Bidirectional, Receiver, Transmitter Sets the port direction. The selection enables or disables the receiver and transmitter supporting logic appropriately.
  • Bidirectional—instantiates both the SDI transmitter and receiver.
  • Receiver—instantiates the SDI receiver
  • Transmitter—instantiates the SDI transmitter.
Transceiver and/or Protocol Combined, Transceiver, Protocol Selects the transceiver or protocol components, or both.
  • Transceiver—includes tx/rx_phy_mgmt/phy_adapter and Native PHY IP. This option is useful if you want to use the same transceiver component to support both SDI and ASI IP cores.
  • Protocol—allows each submodule to be removed or reused across different video standards. The transmitter and receiver data paths are independent from each other.
Note: This option is available only for Arria V, Cyclone V, and Stratix V devices.
Transceiver Options
Transceiver reference clock frequency

148.5/148.35 MHz,

74.25/74.175 MHz,

Selects the transceiver reference clock frequency.

The 74.25/74.175 MHz option is available only for HD-SDI and HD-SDI dual link video standards, and if you select CMU as the TX PLL.

Note: This option is not available if you select ATX PLL.
TX PLL type

CMU, ATX

Selects the transmitter PLL for TX or bidirectional ports.

ATX PLL is useful for bidirectional channels—you can use the ATX PLL as the transmitter PLL instead of the CMU PLL from another channel.

Note: This option is not available if you select ATX PLL.
Dynamic TX clock switching

Off, TX PLL switching, TX PLL reference clock switching

  • Off: Disable dynamic switching
  • TX PLL switching: Instantiates two PLLs, each with a reference input clock
  • TX PLL reference clock switching: Instantiates a PLL with two reference input clocks.
Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates.
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using TX or bidirectional ports, and all video standards except SD-SDI.
Receiver Options
Increase error tolerance level On, Off
  • On: Error tolerance level = 15
  • Off: Error tolerance level = 4

Turn on this option to increase the tolerance level for consecutive missed end of active videos (EAVs), start of active videos (SAVs), or erroneous frames.

CRC error output On, Off
  • On: CRC monitoring (Not applicable for SD-SDI mode)
  • Off: No CRC monitoring (saves logic)
Extract Payload ID (SMPTE ST 352) On, Off
  • On: Extract payload ID
  • Off: No payload ID extraction (saves logic)

You must turn on this option for 3G-SDI, HD SDI dual link, triple-rate, and multi-rate modes. The extracted payload ID is required for consistent detection of the 1080p format.

It is compulsory to turn on this option for design example demonstration when you turn on Convert HD-SDI dual link to 3G-SDI (level B) or Convert 3G-SDI (level B) to HD-SDI dual link.

Rx core clock (rx_coreclk) frequency
  • Agilex™ 7 F-Tile - 100 MHz to 156.25 MHz

  • Arria® 10, Cyclone® 10 GX, and Stratix® 10 - 148.5/148.35 MHz, 297.0/296.70 MHz
Selects the supported clock frequency for the rx_coreclk signal. This option is only available when you select Multi rate (up to 12G-SDI) in Receiver or Bidirectional mode. For other standards, the default frequency is 148.5/148.35 MHz.
Note: This option is only available in Quartus® Prime Pro Edition software
Note: The frequency range - 100 MHz to 156.25 MHz is available in Agilex™ 7 F-Tile in the Quartus® Prime Pro Edition software. Intel recommends to use the same clock as i_csr_clk port on F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP.
Convert HD-SDI dual link to 3G-SDI (level B) On, Off
  • On: Converts to level B (2 × SMPTE ST 292 HD-SDI mapping, including SMPTE ST 372 dual link mapping) for HD-SDI dual link receiver output.
  • Off: No conversion
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using HD-SDI dual link receiver.
Convert 3G-SDI (level B) to HD-SDI dual link On, Off
  • On: Converts to HD-SDI dual link (direct image format mapping) for 3G-SDI receiver output.
  • Off: No conversion
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using 3G-SDI receiver.
Transmitter Options
Insert payload ID (SMPTE ST 352) On, Off
  • On: Insert payload ID
  • Off: No payload ID insertion (saves logic)

Video Streaming Options
Enable active video data protocols AXIS-VVP Full, None
  • Turn on to enable Intel FPGA video streaming interface.
  • Turn off for clocked video interface.
  • Only available when Video standard is set to Multi rate (up to 12G-SDI)
Bits per color sample 10, 12
  • Select the number of bits per color sample.

  • Only available when Enable active video data protocols is set to AXIS-VVP Full.

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