SDI II Intel® FPGA IP User Guide

ID 683133
Date 6/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3. SDI II IP Core Registers

The registers are only available when Enable active video data protocols = AXIS-VVP Full. Each register is either read-only (RO), write-only (WO), or read-write (RW).