SDI II Intel® FPGA IP User Guide

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ID 683133
Date 2/16/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Manual Adaptation Mode 7.1.3.3. TX EQ Settings
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon-MM Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel

The rx_cal_busy and tx_cal_busy signals from the transceiver are from the same internal node and change state concurrently during calibration. Because these signals are from the same internal node, the RX and TX transceivers in the same channel are affected by each other when one transceiver is in calibration. Problems may occur when the RX and TX transceivers in the same channel are required to work independently, because the TX is held in reset when the RX recalibrates or vice versa.

A possible workaround for this problem is to use the transceiver arbiter from the generated design example. For more details about the arbiter's signal interface, refer to the respective design example user guides.

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