Visible to Intel only — GUID: iga1463598464831
Ixiasoft
Visible to Intel only — GUID: iga1463598464831
Ixiasoft
48.5. Example System
The following example provides high-level steps showing how the Avalon® -MM DDR Memory Half-Rate Bridge core is connected in a system. This example assumes that you are familiar with the Platform Designer GUI.
- Add a Nios® II Processor to the system.
- Add a DDR2 SDRAM High-Performance Controller and configure it to full-rate mode.
- Add Avalon® -MM DDR Memory Half-Rate Bridge to the system.
- Configure the parameters of the Avalon® -MM DDR Memory Half-Rate Bridge based on the memory controller. For example, for a 32 MByte DDR memory controller in full rate mode with 8 DQ pins (see ), the parameters should be set as the following:
- Data Width = 16
For a memory controller that has 8 DQ pins, its local interface width is 16 bits. The local interface width and the data width must be the same, therefore data width is set to 16 bits.
- Address Width = 25
For a memory capacity of 32 MBytes, the byte address is 25 bits. Because the host address of the bridge is byte aligned, the address width is set to 25 bits.
- Data Width = 16
- Connect altmemddr_auxhalf to the agent clock interface (clk_s1) of the Half-Rate Bridge.
- Connect altmemddr_sysclk to the host clock interface (clk_m1) of the Half-Rate Bridge.
- Remove all connections between Nios® II processor and the memory controller, if there are any.
- Connect the host interface (m1) of the Avalon® -MM DDR Memory Half-Rate Bridge to the memory controller agent interface.
- Connect the agent interface (s1) of the Avalon® -MM DDR Memory Half-Rate Bridge to the Nios® II processor data_master interface.
- Connect altmemddr_auxhalf to Nios® II processor clock interface.