Advanced SEU Detection Intel® FPGA IP Release Notes

ID 683124
Date 4/01/2024
Public

Altera Advanced SEU Detection IP Core (altera_adv_seu_detection) v14.1

Table 6.  v14.1 December 2014
Description Impact
Added support for double-adjacent SEU sensitivity processing. Initiates an .smh lookup for correctable double-adjacent EDCRC errors instead of identifying such SEU as critical.
Added critical_clear signal to errors interface -
Added busy signal to errors interface For on-chip processing configuration only.