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1.1. About Precision RTL Synthesis Support
1.2. Precision RTL Integration Flow
1.3. Intel Device Family Support
1.4. Precision RTL Generated Files
1.5. Creating and Compiling a Project in the Precision Synthesis Software
1.6. Mapping the Design with Precision RTL
1.7. Synthesizing the Design and Evaluating the Results
1.8. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
1.9. Siemens EDA Precision* RTL Synthesis Support Revision History
1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files
1.8.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files
1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor
1.8.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files
1.8.5. Instantiating Black Box IP Functions With Generated VHDL Files
1.8.6. Inferring Intel FPGA IP Cores from HDL Code
2.1. About Synplify Support
2.2. Synplify Software Integration Flow
2.3. Hardware Description Language Support
2.4. Intel Device Family Support
2.5. Tool Setup
2.6. Synplify Software Generated Files
2.7. Design Constraints Support
2.8. Simulation and Formal Verification
2.9. Synplify Optimization Strategies
2.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
2.11. Synopsys Synplify* Support Revision History
2.12. Intel Quartus Prime Pro Edition User Guide: Third-Party Synthesis Archives
2.10.1.1. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files
2.10.1.2. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files
2.10.1.3. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores
2.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor
2.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files
2.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files
2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
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2.2. Synplify Software Integration Flow
The following steps describe a basic Intel® Quartus® Prime software flow integrating the Synplify software:
- Create Verilog HDL (.v) or VHDL (.vhd) design files.
- Set up a project in the Synplify software and add the HDL design files for synthesis.
- Select a target device and add timing constraints and compiler directives in the Synplify software to help optimize the design during synthesis.
- Synthesize the project in the Synplify software.
- Create an Intel® Quartus® Prime project and import the following files generated by the Synplify software into the Intel® Quartus® Prime software. Use the following files for placement and routing, and for performance evaluation:
- Verilog Quartus Mapping File (.vqm) netlist.
- The Synopsys Constraints Format (.scf) file for Timing Analyzer constraints.
- The .tcl file to set up your Intel® Quartus® Prime project and pass constraints.
Note: Alternatively, you can run the Intel® Quartus® Prime software from within the Synplify software.
- After obtaining place-and-route results that meet your requirements, configure or program the Intel device.
Figure 1. Recommended Design Flow