Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis

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ID 683122
Date 12/12/2023
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Siemens EDA Precision* RTL Synthesis Support 2. Synopsys Synplify* Support A. Intel® Quartus® Prime Pro Edition User Guides
1. Siemens EDA Precision* RTL Synthesis Support x
1.1. About Precision RTL Synthesis Support 1.2. Precision RTL Integration Flow 1.3. Intel Device Family Support 1.4. Precision RTL Generated Files 1.5. Creating and Compiling a Project in the Precision Synthesis Software 1.6. Mapping the Design with Precision RTL 1.7. Synthesizing the Design and Evaluating the Results 1.8. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 1.9. Siemens EDA Precision* RTL Synthesis Support Revision History
1.2. Precision RTL Integration Flow x
1.2.1. Timing Optimization
1.6. Mapping the Design with Precision RTL x
1.6.1. Setting Timing Constraints 1.6.2. Setting Mapping Constraints 1.6.3. Assigning Pin Numbers and I/O Settings 1.6.4. Assigning I/O Registers 1.6.5. Disabling I/O Pad Insertion 1.6.6. Controlling Fan-Out on Data Nets
1.6.5. Disabling I/O Pad Insertion x
1.6.5.1. Preventing the Precision RTL Software from Adding I/O Pads 1.6.5.2. Preventing the Precision RTL Software from Adding an I/O Pad on an Individual Pin
1.7. Synthesizing the Design and Evaluating the Results x
1.7.1. Obtaining Accurate Logic Utilization and Timing Analysis Reports
1.8. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files 1.8.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files 1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor 1.8.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files 1.8.5. Instantiating Black Box IP Functions With Generated VHDL Files 1.8.6. Inferring Intel FPGA IP Cores from HDL Code
1.8.6. Inferring Intel FPGA IP Cores from HDL Code x
1.8.6.1. Multipliers 1.8.6.2. Setting the Use Dedicated Multiplier Option 1.8.6.3. Setting the dedicated_mult Attribute 1.8.6.4. Inferring Multiplier-Accumulators and Multiplier-Adders 1.8.6.5. Controlling DSP Block Inference 1.8.6.6. Inferring RAM and ROM
1.8.6.1. Multipliers x
1.8.6.1.1. Controlling DSP Block Inference for Multipliers
2. Synopsys Synplify* Support x
2.1. About Synplify Support 2.2. Synplify Software Integration Flow 2.3. Hardware Description Language Support 2.4. Intel Device Family Support 2.5. Tool Setup 2.6. Synplify Software Generated Files 2.7. Design Constraints Support 2.8. Simulation and Formal Verification 2.9. Synplify Optimization Strategies 2.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 2.11. Synopsys Synplify* Support Revision History 2.12. Intel Quartus Prime Pro Edition User Guide: Third-Party Synthesis Archives
2.5. Tool Setup x
2.5.1. Specifying the Intel® Quartus® Prime Software Version
2.7. Design Constraints Support x
2.7.1. Running the Intel® Quartus® Prime Software Manually With the Synplify-Generated Tcl Script 2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software
2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software x
2.7.2.1. Individual Clocks and Frequencies 2.7.2.2. Input and Output Delay 2.7.2.3. Multicycle Path 2.7.2.4. False Path
2.9. Synplify Optimization Strategies x
2.9.1. Using Synplify Premier to Optimize Your Design 2.9.2. Using Implementations in Synplify Pro or Premier 2.9.3. Timing-Driven Synthesis Settings 2.9.4. FSM Compiler 2.9.5. Optimization Attributes and Options 2.9.6. Intel-Specific Attributes
2.9.3. Timing-Driven Synthesis Settings x
2.9.3.1. Clock Frequencies 2.9.3.2. Multiple Clock Domains 2.9.3.3. Input and Output Delays 2.9.3.4. Multicycle Paths 2.9.3.5. False Paths
2.9.4. FSM Compiler x
2.9.4.1. FSM Explorer in Synplify Pro and Premier
2.9.5. Optimization Attributes and Options x
2.9.5.1. Retiming in Synplify Pro and Premier 2.9.5.2. Maximum Fan-Out 2.9.5.3. Preserving Nets 2.9.5.4. Register Packing 2.9.5.5. Resource Sharing 2.9.5.6. Preserving Hierarchy 2.9.5.7. Register Input and Output Delays 2.9.5.8. syn_direct_enable 2.9.5.9. I/O Standard
2.9.6. Intel-Specific Attributes x
2.9.6.1. altera_chip_pin_lc 2.9.6.2. altera_io_powerup 2.9.6.3. altera_io_opendrain
2.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
2.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog 2.10.2. Including Files for Intel® Quartus® Prime Placement and Routing Only 2.10.3. Inferring Intel FPGA IP Cores from HDL Code
2.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog x
2.10.1.1. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files 2.10.1.2. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files 2.10.1.3. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores 2.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor 2.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files 2.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files 2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
2.10.3. Inferring Intel FPGA IP Cores from HDL Code x
2.10.3.1. Inferring Multipliers 2.10.3.2. Inferring RAM VHDL Code for Inferred Dual-Port RAM VHDL Code for Inferred Dual-Port RAM Preventing Bypass Logic 2.10.3.3. RAM Initialization 2.10.3.4. Inferring ROM 2.10.3.5. Inferring Shift Registers
2.10.3.1. Inferring Multipliers x
2.10.3.1.1. Resource Balancing 2.10.3.1.2. Controlling the DSP Block Inference 2.10.3.1.3. Signal Level Attribute
Answers to Top FAQs
1. Siemens EDA Precision* RTL Synthesis Support
2. Synopsys Synplify* Support
A. Intel® Quartus® Prime Pro Edition User Guides

2.10.3.2. Inferring RAM

When a RAM block is inferred from an HDL design, the Synplify software uses an Intel FPGA IP core to target the device memory architecture. For some devices, the Synplify software maps directly to memory block device primitives instead of instantiating an IP core in the .vqm file.

Follow these guidelines for the Synplify software to successfully infer RAM in a design:

  • The address line must be at least two bits wide.
  • Resets on the memory are not supported. Refer to the device family documentation for information about whether read and write ports must be synchronous.
  • Some Verilog HDL statements with blocking assignments might not be mapped to RAM blocks, so avoid blocking statements when modeling RAMs in Verilog HDL.

For some device families, the syn_ramstyle attribute specifies the implementation to use for an inferred RAM. You can apply the syn_ramstyle attribute globally to a module or a RAM instance, to specify registers or block_ram values. To turn off RAM inference, set the attribute value to registers.

When inferring RAM for some Intel device families, the Synplify software generates additional bypass logic. This logic is generated to resolve a half-cycle read/write behavior difference between the RTL and post-synthesis simulations. The RTL simulation shows the memory being updated on the positive edge of the clock; the post-synthesis simulation shows the memory being updated on the negative edge of the clock. To eliminate bypass logic, the output of the RAM must be registered. By adding this register, the output of the RAM is seen after a full clock cycle, by which time the update has occurred, thus eliminating the need for bypass logic.

For devices with TriMatrix memory blocks, disable the creation of glue logic by setting the syn_ramstyle value to no_rw_check. Set syn_ramstyle to no_rw_check to disable the creation of glue logic in dual-port mode.

VHDL Code for Inferred Dual-Port RAM

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dualport_ram IS
PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    data_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
    wr_addr, rd_addr: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    we: IN STD_LOGIC);
    clk: IN STD_LOGIC);
END dualport_ram;

ARCHITECTURE ram_infer OF dualport_ram IS
TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECOR (7 DOWNTO 0);
SIGNAL mem; Mem_Type;
SIGNAL addr_reg: STD_LOGIC_VECTOR (6 DOWNTO 0);

BEGIN
    data_out <= mem (CONV_INTEGER(rd_addr));
    PROCESS (clk, we, data_in) BEGIN
        IF (clk='1' AND clk'EVENT) THEN
            IF (we='1') THEN
                mem(CONV_INTEGER(wr_addr)) <= data_in;
            END IF;
        END IF;
    END PROCESS;
END ram_infer;

VHDL Code for Inferred Dual-Port RAM Preventing Bypass Logic 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dualport_ram IS
PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    wr_addr, rd_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    we : IN STD_LOGIC;
    clk : IN STD_LOGIC);
END dualport_ram;

ARCHITECTURE ram_infer OF dualport_ram IS
TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL mem : Mem_Type;
SIGNAL addr_reg : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL tmp_out : STD_LOGIC_VECTOR (7 DOWNTO 0); --output register

BEGIN
    tmp_out <= mem (CONV_INTEGER (rd_addr));
    PROCESS (clk, we, data_in) BEGIN
        IF (clk='1' AND clk'EVENT) THEN
            IF (we='1') THEN
                mem(CONV_INTEGER(wr_addr)) <= data_in;
            END IF;
            data_out <= tmp_out; --registers output preventing
                                 -- bypass logic generation
        END IF;
    END PROCESS;
END ram_infer;
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