JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.5.1.1. Platform Designer System Component

The Platform Designer system instantiates the JESD204B IP core data path and supporting peripherals.

Figure 9.  Platform Designer System for System Console Control Design Example
Figure 10.  Platform Designer System for Nios® Control Design Example

The top level Platform Designer system instantiates the following modules:

  • Platform Designer system
    • JESD204B subsystem
    • JTAG to Avalon® master bridge—for System Console Control design example only
    • Nios® subsystem— Nios® Control design example only
    • Parallel I/O (PIO)
    • ATX PLL
    • Core PLL
    • PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
    • Serial Port Interface (SPI)—master module

The following are the key features of the top level Platform Designer system:

  • Supports 2 design example types:
    • System Console control
    • Nios® control
  • Supports 3 data path types:
    • Duplex—Both TX and RX data paths present
    • Simplex TX—Only TX data path present
    • Simplex RX—Only RX data path present
  • Supports transceiver dynamic reconfiguration enabled mode:
    • When enabled, connects the JTAG to Avalon® master bridge (System Console control) or Nios® subsystem ( Nios® control) module to the following interfaces:
      • Transceiver PHY reconfiguration interface
      • ATX PLL reconfiguration interface
      • Core PLL reconfiguration controller
    • When disabled, reconfiguration interfaces not present in design example
  • The JESD204B subsystem, PLL reconfiguration controller, ATX PLL dynamic reconfiguration interface, parallel I/O and SPI master modules are connected to the JTAG to Avalon® master bridge (System Console control) or Nios® subsystem ( Nios® control) module via the Avalon® memory-mapped interface.
  • JTAG to Avalon® master bridge provides a link to the user via System Console. You can control the behavior of the design example via Tcl scripts executed in the System Console interface.
  • Nios® subsystem provides a way for the user to control the behavior of the design example using embedded C programming.
  • TX data path flow:
    • Input: 32-bit per transceiver lane Avalon® streaming input from assembler (TX transport layer)
    • Output: TX serial data
  • RX data path flow:
    • Input: RX serial data from either external converter source or internal serial loopback
    • Output: 32-bit per transceiver lane Avalon® streaming output to deassembler (RX transport layer)
  • SPI master module links out to the SPI configuration interface of external converters via a 3- or 4-wire SPI interconnect (depending on Generate 3-Wire SPI Module setting).
  • SPI master module handles the serial transfer of configuration data to the SPI interface on the converter end
  • The ATX PLL generates the serial clock for clocking the TX serial data
    • ATX PLL module generated for duplex and simplex TX data path only
    • ATX PLL reconfiguration interface only present when transceiver dynamic reconfiguration option is enabled.
    • When present, ATX PLL reconfiguration interface connects to the JTAG to Avalon® master bridge (System Console control)or Nios® subsystem ( Nios® control) module via the Avalon® memory-mapped interface.
  • The core PLL generates the following clocks for the system:
    • Link clock
    • Frame clock
Figure 11. Top Level Platform Designer Address Map

Section Content
JESD204B Subsystem in Platform Designer
Parallel I/O
ATX PLL
Core PLL
SPI Master
Nios Subsystem

Level Two Title